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ADVANCE INFORMATION
MICRONAS
VCT 38xxA Video/Controller/Teletext IC Family
Edition Oct. 17, 2000 6251-518-1AI
MICRONAS
VCT 38xxA
Contents Page Section Title
ADVANCE INFORMATION
7
8
8 8 8 8 8 8
1.
1.1.
1.1.1. 1.1.2. 1.1.3. 1.1.4. 1.1.5. 1.1.6.
Introduction
Features
Video Features Microcontroller Features OSD Features Teletext Features Audio Features General Features
9 10
1.2. 1.3.
Chip Architecture System Application
11
11 11
11 11 11 11 12 12
2.
2.1. 2.2.
2.2.1. 2.2.2. 2.2.3. 2.2.4. 2.2.5. 2.2.6.
Video Processing
Introduction Video Front-end
Input Selector Clamping Automatic Gain Control Analog-to-Digital Converters Digitally Controlled Clock Oscillator Analog Video Output
12 13
13 14 14 14 14 14 15 15 16 16
2.3. 2.4.
2.4.1. 2.4.2. 2.4.3. 2.4.4. 2.4.5. 2.4.6. 2.4.7. 2.4.8. 2.4.9. 2.4.10.
Adaptive Comb Filter Color Decoder
IF-Compensation Demodulator Chrominance Filter Frequency Demodulator Burst Detection / Saturation Control Color Killer Operation Automatic Standard Recognition PAL Compensation/ 1-H Comb Filter Luminance Notch Filter Skew Filtering
16 16 17 17 18 18
18 18 19 21 21 21 21 22 22 22 22 23 23 23
2.5. 2.6. 2.7. 2.8. 2.9. 2.10.
2.10.1. 2.10.2. 2.10.3. 2.10.4. 2.10.5. 2.10.6. 2.10.7. 2.10.8. 2.10.9. 2.10.10. 2.10.11. 2.10.12. 2.10.13. 2.10.14.
Horizontal Scaler Black-line Detector Test Pattern Generator Video Sync Processing Macrovision Detection Display Processing
Luma Contrast Adjustment Black-Level Expander Dynamic Peaking Digital Brightness Adjustment Soft Limiter Chroma Interpolation Chroma Transient Improvement Inverse Matrix RGB Processing OSD Color Look-up Table Picture Frame Generator Priority Decoder Scan Velocity Modulation Display Phase Shifter
2
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VCT 38xxA
Contents, continued Page
25
25 26 27 27 27
Section
2.11.
2.11.1. 2.11.2. 2.11.3. 2.11.4. 2.11.5.
Title
Video Back-end
CRT Measurement and Control SCART Output Signal Average Beam Current Limiter Analog RGB Insertion Fast-Blank Monitor
29
29 29 29 30 30 31
2.12.
2.12.1. 2.12.2. 2.12.3. 2.12.4. 2.12.5. 2.12.6.
Synchronization and Deflection
Deflection Processing Angle and Bow Correction Horizontal Phase Adjustment Vertical and East/West Deflection EHT Compensation Protection Circuitry
31 31 32
32 44 46
2.13. 2.14. 2.15.
2.15.1. 2.15.1.1. 2.15.1.2.
Reset Function Standby and Power-On I2C Bus Slave Interface
Control and Status Registers Scaler Adjustment Calculation of Vertical and East-West Deflection Coefficients
47
47 47 47 49 49
49 50 50 52 52
3.
3.1. 3.2. 3.3. 3.4. 3.5.
3.5.1. 3.5.2. 3.5.3. 3.5.4. 3.5.5.
Text and OSD Processing
Introduction SRAM Interface Text Controller Teletext Acquisition Teletext Page Management
Memory Manager Memory Organization Page Table Ghost Row Organization Subpage Manager
53 55 57
58 59 60 61 62 63
3.6. 3.7. 3.8.
3.8.1. 3.8.2. 3.8.3. 3.8.4. 3.8.5. 3.8.6.
WST Display Controller Display Memory Character Generator
Character Code Mapping Character Font ROM Latin Font Mapping Cyrillic Font Mapping Arabic Font Mapping Character Font Structure
64 66 67 68 76 82
82 82 83 83 83 84
3.9. 3.10. 3.11. 3.12. 3.13. 3.14.
3.14.1. 3.14.1.1. 3.14.1.2. 3.14.1.3. 3.14.1.4. 3.14.1.5.
National Character Mapping Four-Color Mode OSD Layer Command Language I/O Register I2C-Bus Slave Interface
Subaddressing CPU Subaddressing DRAM Subaddressing Command Subaddressing Data Subaddressing Hardware Identification
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Contents, continued Page Section Title
ADVANCE INFORMATION
85
85 85 85 85
4.
4.1. 4.2. 4.3. 4.4.
Audio Processing
Introduction Input Select Volume Control I2C-Bus Slave Interface
86
86 86
86
5.
5.1. 5.2.
5.2.1.
TV Controller
Introduction CPU
CPU Slow Mode
87
87 87
5.3.
5.3.1. 5.3.2.
RAM and ROM
Address Map Bootloader
87 89 90 90
90 90 91 91 91 92 92 93 94 94 94
5.4. 5.5. 5.6. 5.7.
5.7.1. 5.7.2. 5.7.2.1. 5.7.2.2. 5.7.3. 5.7.3.1. 5.7.3.2. 5.7.3.3. 5.7.4. 5.7.5. 5.7.6.
Control Register Standby Registers Test Registers Reset Logic
Alarm Function Software Reset From Standby into Normal Mode From Normal into Standby Mode Internal Reset Sources Supply Supervision Clock Supervision Watchdog External Reset Sources Summary of Module Reset States Reset Registers
95
95
5.8.
5.8.1.
Memory Banking
Banking Register
96
98
5.9.
5.9.1.
DMA Interface
DMA Registers
99
99 99 99 99 99 101 101 103 103 104 106
5.10.
5.10.1. 5.10.2. 5.10.3. 5.10.4. 5.10.5. 5.10.6. 5.10.7. 5.10.8. 5.10.8.1. 5.10.9. 5.10.10.
Interrupt Controller
Features General Initialization Operation Inactivation Precautions Interrupt Registers Interrupt Assignment Interrupt Multiplexer Port Interrupt Module Interrupt Timing
107
107 107 107 108 108
5.11.
5.11.1. 5.11.2. 5.11.3. 5.11.4. 5.11.5.
Memory Patch Module
Features General Initialization Patch Operation Patch Registers
109
111
5.12.
5.12.1.
I2C-Bus Master Interface
I2C Bus Master Interface Registers
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VCT 38xxA
Contents, continued Page
113
113 113 114
Section
5.13.
5.13.1. 5.13.2. 5.13.3.
Title
Timer T0 and T1
Features Operation Timer Registers
115
115 116 116 116 117 118
5.14.
5.14.1. 5.14.2. 5.14.3. 5.14.3.1. 5.14.4. 5.14.5.
Capture Compare Module (CAPCOM)
Features Initialization Operation of CCC Operation of Subunit Inactivation CAPCOM Registers
120
120 120 120 120 120
5.15.
5.15.1. 5.15.2. 5.15.3. 5.15.4. 5.15.5.
Pulse Width Modulator
Features General Initialization Operation PWM Registers
121
121 121 122 122 122
5.16.
5.16.1. 5.16.2. 5.16.3. 5.16.4. 5.16.5.
Tuning Voltage Pulse Width Modulator
Features General Initialization Operation TVPWM Registers
123
123 123 124 124 125
5.17.
5.17.1. 5.17.2. 5.17.3. 5.17.4. 5.17.5.
A/D Converter (ADC)
Features Operation Measurement Errors Comparator ADC Registers
126
126 127 127 128 128 129 129 130 130 131 131
5.18.
5.18.1. 5.18.2. 5.18.2.1. 5.18.2.2. 5.18.3. 5.18.4. 5.18.4.1. 5.18.5. 5.18.5.1. 5.18.6. 5.18.6.1.
Ports
Port Assignment Universal Ports P1 to P3 Features Universal Port Mode Universal Port Registers I2C Ports P40 and P41 Features Audio Ports P42 to P46 Features CLK20 Output Port Features
132
5.19.
I/O Register Cross Reference
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Contents, continued Page Section Title
ADVANCE INFORMATION
136
136 138 142 144 145 147 150
150 150 150 151 152 153 153 153 154 154 155 155 155 156 158 159 159 159 159 160 160 160 160 161 161 164 164 165 165 166
6.
6.1. 6.2. 6.3. 6.4. 6.5. 6.6. 6.7.
6.7.1. 6.7.2. 6.7.2.1. 6.7.2.2. 6.7.2.3. 6.7.3. 6.7.3.1. 6.7.3.2. 6.7.3.3. 6.7.3.4. 6.7.3.5. 6.7.3.6. 6.7.3.7. 6.7.3.8. 6.7.3.9. 6.7.3.10. 6.7.3.11. 6.7.3.12. 6.7.3.13. 6.7.3.14. 6.7.3.15. 6.7.3.16. 6.7.3.17. 6.7.3.18. 6.7.3.19. 6.7.3.20. 6.7.3.21. 6.7.3.22. 6.7.3.23. 6.7.3.24.
Specifications
Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions for PSDIP64 package Pin Descriptions for PMQFP128 package Pin Configuration Pin Circuits Electrical Characteristics
Absolute Maximum Ratings Recommended Operating Conditions General Recommendations Analog Input and Output Recommendations Recommended Crystal Characteristics Characteristics General Characteristics Test Input Reset Input I2C Bus Interface 20-MHz Clock Output Analog Video Output A/D Converter Reference Analog Video Front-End and A/D Converters Analog RGB and FB Inputs Horizontal Flyback Input Horizontal Drive Output Vertical Safety Input Vertical Protection Input Vertical and East/West D/A Converter Output Interlace Output Sense A/D Converter Input Range Switch Output D/A Converter Reference Analog RGB Outputs, D/A Converters Scan Velocity Modulation Output Analog Audio Inputs and Outputs ADC Input Port Universal Port Memory Port
167 171 171 172
7. 8. 9. 10.
Application Glossary of Abbreviations References Data Sheet History
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ADVANCE INFORMATION
VCT 38xxA
Video/Controller/Teletext IC Family Release Note: This data sheet describes functions and characteristics of the VCT 38xxA-B2.
1. Introduction The VCT 38xxA is an IC family of high-quality singlechip TV processors. Modular design and a submicron technology allow the economic integration of features in all classes of TV sets. The VCT 38xxA family is based on functional blocks contained and approved in existing products like VDP 3120B, TPU 3050S, and CCZ 3005K. Each member of the family contains the entire video, display and deflection processing for 4:3 and 16:9 50/ 60-Hz TV sets. The integrated microcontroller is supported by a powerful OSD generator with integrated teletext acquisition which can be upgraded with onchip page memory. With volume control and audio input select the basic audio features for mono TV sets are integrated. An overview of the VCT 38xxA singlechip TV processor family is given in Fig. 1-1 on page 7. The VCT 38xxA family offers a rich feature set, covering the whole range of state-of-the-art 50/60-Hz TV applications.
Picture Improvements (Color Transient Improv., Soft Limiter, Black-Level Expander)
8-Bit Microcontroller 96 kB ROM, 1 kB RAM Flash Option Color Decoder Tube Control OSD Generator Audio Control
Adaptive Comb Filter
VCT 38xxA Family VCT 3801A VCT 3802A VCT 3803A VCT 3804A VCT 3811A VCT 3831A VCT 3832A VCT 3833A VCT 3834A
PMQFP128 PMQFP128
Fig. 1-1: VCT 38xxA family overview
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ext. Prog. Memory
ext. Page Memory
Panorama Scaler
10 Page Teletxt
1 Page Teletxt
7
VCT 38xxA
1.1. Features 1.1.1. Video Features - four composite video inputs, two S-VHS inputs - analog YCrCb input - composite video monitor - multistandard color decoder (1 crystal) - multistandard sync decoder - black-line detector - adaptive 2H comb filter Y/C separator - horizontal scaling (0.25 to 4) - Panoramavision - black-level expander - dynamic peaking - soft limiter (gamma correction) - color transient improvement - programmable RGB matrix - analog RGB/Fastblank input - half-contrast switch - picture frame generator - scan velocity modulation output - high-performance H/V deflection - angle and bow correction - separate ADC for tube measurements - EHT compensation 1.1.4. Teletext Features 1.1.3. OSD Features - 3 kB OSD RAM on chip - WST level 1.5 compliant
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- WST level 2 parallel attributes - 32 foreground/background colors - programmable color look-up table - 1024 mask programmable characters - 24 national languages (Latin, Cyrillic, Greek, Arabic, Farsi, Hebrew) - character matrix 8x8, 8x10, 8x13, 10x8, 10x10, 10x13 - vertical soft scroll - 4-color mode for user font
- four programmable video inputs - acquisition is independent from display part - adaptive data slicer - signal quality detection - WST, PDC, VPS, and WSS acquisition - high-level command language - EPG, FLOF, and TOP support - 10 pages memory on chip - up to 500 pages with external SRAM
1.1.2. Microcontroller Features - 8-bit, 10-MHz CPU (65C02) - 96 kB program ROM on chip - 1 kB program RAM on chip - memory banking - 16-input, 16-level interrupt controller - patch modul for 10 ROM locations - two 16-bit reloadable timers - capture compare modul - watchdog timer - 14-bit PWM for voltage synthesis - four 8-bit PWMs - 10-bit ADC with 15:1 input MUX - I2C bus master interface - 24 programmable I/O ports
1.1.5. Audio Features - three mono inputs - two mono outputs - programmable channel select - volume control for one mono channel
1.1.6. General Features - submicron CMOS technology - low-power standby mode - single 20.25-MHz crystal - 64-pin PSDIP package - 128-pin PMQFP package - emulator chip for software development
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VCT 38xxA
1.2. Chip Architecture
VSUPAF
GNDAF
VSUPD
SENSE 2
GNDD
VCT 38xx
Comb Filter
2
2
VIN CIN VOUT
4 3
Video Front-end
Color Decoder
Panorama Scaler
Display Processor Pict.Improv.
RSW GNDM VRD XREF 3
SGND
VERT EW PROT HOUT
HFLB
VRT
Video Back-end
RGBOUT SVM
4
RGBIN VSUPAB GNDAB
Video
8
I2C MSync Color, Prio VSync
2
Audio
AOUT AIN
3
BE
I2C Master CPU 8-bit PWM 14-bit PWM 15:1 Mux 10-bit ADC 2 Timer 2 CapCom
2
I2C
TPU 24 kB ROM 24 kB
DMA
RDY
3 3 kB kB OSD RAM OSD
1 kB CPU RAM
Reset Logic
RESQ TEST
16 kB Text RAM
31 ADB, DB, CB
96 kB CPU ROM
Watchdog 24 IO Ports
12 VSUPP1 Pxy GNDP1
Clock Oscillator
XTAL1 XTAL2
CLK20
VSUPS
Fig. 1-2: Block diagram of the VCT 38xxA (shaded blocks are optional)
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GNDS
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VCT 38xxA
1.3. System Application
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Analog RGB
R G B FB 20.25 MHz
Analog Audio
Tuner/SCART/FrontAV
CVBS1 Loudspeaker
Analog Video
CVBS2 Y Cr
VCT 38xxA
Cb
Y C CRT
WE2 OE2 CE DB
CE OE1 WE1
512 kB SRAM
ADB
512 kB ROM/ FLASH
optional memory extension
Fig. 1-3: Single-chip TV with VCT 38xxA
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VCT 38xxA
2.2.2. Clamping The composite video input signals are AC-coupled to the IC. The clamping voltage is stored on the coupling capacitors and is generated by digitally controlled current sources. The clamping level is the back porch of the video signal. S-VHS chrominance is also AC-coupled. The input pin is internally biased to the center of the ADC input range. The chrominance inputs for YCrCb need to be AC-coupled by 220 nF clamping capacitors. It is strongly recommended to use 5-MHz anti-alias low-pass filters on each input. Each channel is sampled at 10.125 MHz with a resolution of 8 bit and a clamping level of 128.
2. Video Processing 2.1. Introduction The VCT 38xxA includes complete video, display, and deflection processing. In the following sections the video processing part of the VCT 38xxA will be named VDP for short. All processing is done digitally, the video front-end and video back-end are interfacing to the analog world. Most functions of the VDP can be controlled by software via I2C bus slave interface (see Section 2.15. on page 32).
2.2. Video Front-end This block provides the analog interfaces to all video inputs and mainly carries out analog-to-digital conversion for the following digital video processing. A block diagram is given in Fig. 2-1. Most of the functional blocks in the front-end are digitally controlled (clamping, AGC, and clock-DCO). The control loops are closed by the Fast Processor (`FP') embedded in the video decoder.
2.2.3. Automatic Gain Control A digitally working automatic gain control adjusts the magnitude of the selected baseband by +6/-4.5 dB in 64 logarithmic steps to the optimal range of the ADC. The gain of the video input stage including the ADC is 213 steps/V with the AGC set to 0 dB. The gain of the chrominance path in the YCrCb mode is fix and adapted to a nominal amplitude of 0.7 Vpp. However, if an overflow of the ADC occurs an extended signal range from 1 Vpp can be selected. 2.2.4. Analog-to-Digital Converters Two ADCs are provided to digitize the input signals. Each converter runs with 20.25 MHz and has 8 bit resolution. An integrated bandgap circuit generates the required reference voltages for the converters. The two ADCs are of a 2-stage subranging type.
2.2.1. Input Selector Up to seven analog inputs can be connected. Four inputs are for input of composite video or S-VHS luma signal. These inputs are clamped to the sync back porch and are amplified by a variable gain amplifier. Two chroma inputs can be used for connection of S-VHS carrier-chrominance signal. These inputs are internally biased and have a fixed gain amplifier. For analog YCrCb signals (e.g. from DVD players) one of the selected luminance inputs is used together with CBIN and CRIN inputs. CVBS/Y CVBS/Y CVBS/Y CVBS/Y CVBS/Y Chroma Chroma VOUT VIN1 VIN2 Input Mux VIN3 VIN4 CIN1 CIN2 CRIN Clamp Chroma CBIN Clamp Gain Bias
3
AGC +6/-4.5 dB
ADC
digital CVBS or Luma
ADC
digital Chroma System Clocks
mux
Reference Generation
DVCO 150 ppm
Frequency
20.25 MHz
Fig. 2-1: Video front-end
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2.2.5. Digitally Controlled Clock Oscillator The clock generation is also a part of the analog frontend. The crystal oscillator is controlled digitally by the control processor. The clock frequency can be adjusted within 150 ppm. 2.2.6. Analog Video Output The input signal of the Luma ADC is available at the analog video output pin. The signal at this pin must be buffered by a source follower. The output voltage is 2 V, thus the signal can be used to drive a 75- line. The magnitude is adjusted with an AGC in 8 steps together with the main AGC.
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The comb filter uses the middle line as reference, therefore, the comb filter delay is one line. If the comb filter is switched off, the delay lines are used to pass the luma/ chroma signals from the A/D converters to the luma/ chroma outputs. Thus, the comb filter delay is always one line. Various parameters of the comb filter are adjustable, hence giving to the user the ability to adjust his own desired picture quality. Two parameters (KY, KC) set the global gain of luma and chroma comb separately; these values directly weigh the adaption algorithm output. In this way, it is possible to obtain a luma/chroma separation ranging from standard notch/bandpass to full comb decoding. The parameter KB allows to choose between the two proposed comb booster modes. This so-called feature widely improves vertical high-to-low frequency transitions areas, the typical example being a multiburst to DC change. For KB=0, this improvement is kept moderate, whereas, in case of KB=1, it is maximum, but the risk to increase the "hanging dots" amount for some given color transitions is higher. Using the default setting, the comb filter has separate luma and chroma decision algorithms; however, it is possible to switch the chroma comb factor to the current luma adaption output by setting CC to 1. Another interesting feature is the programmable limitation of the luma comb amount; proper limitation, associated to adequate luma peaking, gives rise to an enhanced 2-D resolution homogeneity. This limitation is set by the parameter CLIM, ranging from 0 (no limitation) to 31 (max. limitation). The DAA parameter (1:off, 0:on) is used to disable/ enable a very efficient built-in "rain effect" suppressor; many comb filters show this side effect which gives some vertical correlation to a 2-D uniform random area, due to the vertical filtering. This unnatural-looking phenomenon is mostly visible on tuner images, since they are always corrupted by some noise; and this looks like rain.
2.3. Adaptive Comb Filter The adaptive comb filter is used for high-quality luminance/chrominance separation for PAL or NTSC signals. The comb filter improves the luminance resolution (bandwidth) and reduces interferences like cross-luminance and cross-color artifacts. The adaptive algorithm can eliminate most of the mentioned errors without introducing new artifacts or noise. A block diagram of the comb filter is shown in Fig. 2-2. The filter uses two line delays to process the information of three adjacent video lines. To have a fixed phase relationship of the color subcarrier in the three channels, the system clock (20.25 MHz) is fractionally locked to the color subcarrier. This allows the processing of all color standards and substandards using a single crystal frequency. The CVBS signal in the three channels is filtered at the subcarrier frequency by a set of bandpass/notch filters. The output of the three channels is used by the adaption logic to select the weighting that is used to reconstruct the luminance/chrominance signal from the 4 bandpass/notch filter signals. By using soft mixing of the 4 signals switching artifacts of the adaption algorithm are completely suppressed.
CVBS Input 1H Delay Line Bandpass/ Notch Filter
Luma / Chroma Mixers Adaption Logic
Bandpass Filter
Luma Output
Chroma Output
1H Delay Line Chroma Input
Bandpass Filter
Fig. 2-2: Block diagram of the adaptive comb filter (PAL mode)
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If the adaptive comb filter is used for luma chroma separation, the color decoder uses the S-VHS mode processing. The output of the color decoder is YCrCb in a 4:2:2 format.
2.4. Color Decoder In this block, the standard luma/chroma separation and multi-standard color demodulation is carried out. The color demodulation uses an asynchronous clock, thus allowing a unified architecture for all color standards. A block diagram of the color decoder is shown in Fig. 2-3. The luma as well as the chroma processing, is shown here. The color decoder provides also some special modes, e.g. wide band chroma format which is intended for S-VHS wide bandwidth chroma.
Luma / CVBS
Notch Filter
Luma
MUX
1 H Delay
CrossSwitch
Chroma
ACC MUX IF Compensation Mixer DC-Reject Low-pass Filter Phase/Freq Demodulator
Chroma
ColorPLL/ColorACC
Fig. 2-3: Color decoder
2.4.1. IF-Compensation With off-air or mistuned reception, any attenuation at higher frequencies or asymmetry around the color subcarrier is compensated. Four different settings of the IF-compensation are possible: - flat (no compensation) - 6 dB/octave - 12 dB/octave - 10 dB/MHz The last setting gives a very large boost to high frequencies. It is provided for SECAM signals that are decoded using a SAW filter specified originally for the PAL standard.
Fig. 2-4: Frequency response of chroma IF-compensation
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VCT 38xxA
2.4.2. Demodulator The entire signal (which might still contain luma) is now quadrature-mixed to the baseband. The mixing frequency is equal to the subcarrier for PAL and NTSC, thus achieving the chroma demodulation. For SECAM, the mixing frequency is 4.286 MHz giving the quadrature baseband components of the FM modulated chroma. After the mixer, a low-pass filter selects the chroma components; a downsampling stage converts the color difference signals to a multiplexed half-rate data stream. The subcarrier frequency in the demodulator is generated by direct digital synthesis; therefore, substandards such as PAL 3.58 or NTSC 4.43 can also be demodulated.
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2.4.4. Frequency Demodulator The frequency demodulator for demodulating the SECAM signal is implemented as a CORDIC structure. It calculates the phase and magnitude of the quadrature components by coordinate rotation. The phase output of the CORDIC processor is differentiated to obtain the demodulated frequency. After the deemphasis filter, the Dr and Db signals are scaled to standard CrCb amplitudes and fed to the crossover switch.
2.4.5. Burst Detection / Saturation Control In the PAL/NTSC-system the burst is the reference for the color signal. The phase and magnitude outputs of the CORDIC are gated with the color key and used for controlling the phase-locked-loop (APC) of the demodulator and the automatic color control (ACC) in PAL/ NTSC. The ACC has a control range of +30...-6 dB. Color saturation can be selected once for all color standards. In PAL/NTSC it is used as reference for the ACC. In SECAM the necessary gains are calculated automatically. For SECAM decoding, the frequency of the burst is measured. Thus, the current chroma carrier frequency can be identified and is used to control the SECAM processing. The burst measurements also control the color killer operation; they are used for automatic standard detection as well.
2.4.3. Chrominance Filter The demodulation is followed by a low-pass filter for the color difference signals for PAL/NTSC. SECAM requires a modified low-pass function with bell-filter characteristic. At the output of the low-pass filter, all luma information is eliminated. The low-pass filters are calculated in time multiplex for the two color signals. Three bandwidth settings (narrow, normal, broad) are available for each standard. For PAL/NTSC, a wide band chroma filter can be selected. This filter is intended for high bandwidth chroma signals, e.g. a non-standard wide bandwidth S-VHS signal.
2.4.6. Color Killer Operation The color killer uses the burst-phase/burst-frequency measurement to identify a PAL/NTSC or SECAM color signal. For PAL/NTSC, the color is switched off (killed) as long as the color subcarrier PLL is not locked. For SECAM, the killer is controlled by the toggle of the burst frequency. The burst amplitude measurement is used to switch-off the color if the burst amplitude is below a programmable threshold. Thus, color will be killed for very noisy signals. The color amplitude killer has a programmable hysteresis.
PAL/NTSC
SECAM
Fig. 2-5: Frequency response of chroma filters
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VCT 38xxA
2.4.7. Automatic Standard Recognition
CVBS
The burst-frequency measurement is also used for automatic standard recognition (together with the status of horizontal and vertical locking) thus allowing a completely independent search of the line and color standard of the input signal. The following standards can be distinguished: PAL B,G,H,I; NTSC M; SECAM; NTSC 44; PAL M; PAL N; PAL 60 For a preselection of allowed standards, the recognition can be enabled/disabled via I2C bus for each standard separately. If at least one standard is enabled, the VCT 38xxA regularly checks the horizontal and vertical locking of the input signal and the state of the color killer. If an error exists for several adjacent fields a new standard search is started. Depending on the measured line number and burst frequency, the current standard is selected. For error handling the recognition algorithm delivers the following status information: - search active (busy) - search terminated, but failed - found standard is disabled - vertical standard invalid - no color found
8
Notch filter Chroma Process.
Y Cr C b
Luma
8
Y
Chroma Process.
chroma
8
Cr C b
a) conventional
CVBS
8 Notch filter
b) S-VHS
Y
Chroma Process.
1H Delay
Cr C b
c) compensated
CVBS
8 1H Delay Notch filter
Y
Chroma Process.
Cr C b
d) comb filter Fig. 2-6: NTSC color decoding options
CVBS
8
Notch filter
Y
Chroma Process.
1H Delay
Cr C b
a) conventional
Luma Y
2.4.8. PAL Compensation/1-H Comb Filter The color decoder uses one fully integrated delay line. Only active video is stored. The delay line application depends on the color standard: - NTSC: - PAL: 1-H comb filter or color compensation color compensation
8
Chroma
8
Chroma Process.
1H Delay
Cr C b
b) S-VHS Fig. 2-7: PAL color decoding options
- SECAM: crossover switch In the NTSC compensated mode, (Fig. 2-6c), the color signal is averaged for two adjacent lines. Thus, cross-color distortion and chroma noise is reduced. In the NTSC comb filter mode, (Fig. 2-6d), the delay line is in the composite signal path, thus allowing reduction of cross-color components, as well as cross-luminance. The loss of vertical resolution in the luminance channel is compensated by adding the vertical detail signal with removed color information.
CVBS
8
Notch filter
Y
Chroma Process.
1H Delay
MUX
Cr C b
Fig. 2-8: SECAM color decoding
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VCT 38xxA
2.4.9. Luminance Notch Filter If a composite video signal is applied, the color information is suppressed by a programmable notch filter. The position of the filter center frequency depends on the subcarrier frequency for PAL/NTSC. For SECAM, the notch is directly controlled by the chroma carrier frequency. This considerably reduces the cross-luminance. The frequency responses for all three systems are shown in Fig. 2-9.
10 0 dB
ADVANCE INFORMATION
2.5. Horizontal Scaler The 4:2:2 YCrCb signal from the color decoder is processed by the horizontal scaler. The scaler block allows a linear or nonlinear horizontal scaling of the input video signal in the range of 0.25 to 4. Nonlinear scaling, also called "Panoramavision", provides a geometrical distortion of the input picture. It is used to fit a picture with 4:3 format on a 16:9 screen by stretching the picture geometry at the borders. Also, the inverse effect can be produced by the scaler. A summary of scaler modes is given in Table 2-1. The scaler contains a programmable decimation filter, a 1-line FIFO memory, and a programmable interpolation filter. The scaler input filter is also used for pixel skew correction (see Section 2.4.10. on page 16). The decimator/interpolator structure allows optimal use of the FIFO memory. The controlling of the scaler is done by the internal Fast Processor.
-10
-20
-30
-40 0 2 4 6 8 10
MHz
Table 2-1: Scaler modes Mode Compression 4:3 16:9 Panorama 4:3 16:9 Zoom 4:3 4:3 Scale Factor 0.75 linear nonlinear compr 1.33 linear Description 4:3 source displayed on a 16:9 tube, with side panels 4:3 source displayed on a 16:9 tube, Borders distorted Letterbox source (PAL+) displayed on a 4:3 tube, vertical overscan with cropping of side panels Letterbox source (PAL+) displayed on a 4:3 tube, vertical overscan, borders distorted, no cropping
PAL/NTSC notch filter
dB
10 0
-10
-20
-30
-40 0 2 4 6 8 10
MHz
SECAM notch filter Fig. 2-9: Frequency responses of the luma notch filter for PAL, NTSC, SECAM Panorama 4:3 4:3 nonlinear zoom
2.4.10.Skew Filtering The system clock is free-running and not locked to the TV line frequency. Therefore, the ADC sampling pattern is not orthogonal. The decoded YCrCb signals are converted to an orthogonal sampling raster by the skew filters, which are part of the scaler block. The skew filters allow the application of a group delay to the input signals without introducing waveform or frequency response distortion. The amount of phase shift of this filter is controlled by the horizontal PLL1. The accuracy of the filters is 1/32 clocks for luminance and 1/4 clocks for chroma. Thus the 4:2:2 YCrCb data is in an orthogonal pixel format even in the case of nonstandard input signals such as VCR.
2.6. Black-line Detector In case of a letterbox format input video, e.g. Cinemascope, PAL+ etc., black areas at the upper and lower part of the picture are visible. It is suitable to remove or reduce these areas by a vertical zoom and/or shift operation. The VCT 38xxA supports this feature by a letterbox detector. The circuitry detects black video lines by measuring the signal amplitude during active video. For every field the number of black lines at the upper and lower part of the picture are measured, compared to the previous measurement and the minima are stored in the I2C-register BLKLIN. To adjust the picture
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sures the falling edge of sync, as well as the integrated sync pulse. The sync phase error is filtered by a phase-locked loop that is computed by the FP. All timing in the front-end is derived from a counter that is part of this PLL, and it thus counts synchronously to the video signal. A separate hardware block measures the signal back porch and also allows gathering the maximum/minimum of the video signal. This information is processed by the FP and used for gain control and clamping. For vertical sync separation, the sliced video signal is integrated. The FP uses the integrator value to derive vertical sync and field information. The information extracted by the video sync processing is multiplexed onto the hardware front sync signal (FSY) and is distributed to the rest of the video processing system. The data for the vertical deflection, the sawtooth, and the East-West correction signal is calculated by the VCT 38xxA. The data is buffered in a FIFO and transferred to the back-end by a single wire interface. Frequency and phase characteristics of the analog video signal are derived from PLL1. The results are fed to the scaler unit for data interpolation and orthogonalization and to the clock synthesizer for line-locked clock generation. Horizontal and vertical syncs are latched with the line-locked clock.
amplitude, the external controller reads this register, calculates the vertical scaling coefficient and transfers the new settings, e.g. vertical sawtooth parameters, horizontal scaling coefficient etc., to the VCT 38xxA. Letterbox signals containing logos on the left or right side of the black areas are processed as black lines, while subtitles, inserted in the black areas, are processed as non-black lines. Therefore, the subtitles are visible on the screen. To suppress the subtitles, the vertical zoom coefficient is calculated by selecting the larger number of black lines only. Dark video scenes with a low contrast level compared to the letterbox area are indicated by the BLKPIC bit.
2.7. Test Pattern Generator The YCrCb outputs can be switched to a test mode where YCrCb data are generated digitally in the VCT 38xxA. Test patterns include luma/chroma ramps and flat fields.
2.8. Video Sync Processing Fig. 2-10 shows a block diagram of the front-end sync processing. To extract the sync information from the video signal, a linear phase low-pass filter eliminates all noise and video contents above 1 MHz. The sync is separated by a slicer; the sync phase is measured. A variable window can be selected to improve the noise immunity of the slicer. The phase comparator mea-
PLL1
low-pass 1 MHz & sync slicer video input Front-end Timing Clamp & Signal Meas. clamping, colorkey, FIFO_write Clock Synthesizer Syncs Clock H/V Syncs Horizontal Sync Separation Phase Separator & Low-pass counter Front Sync Generator Front Sync Skew Vblank Field
Vertical Sync Separation
Sawtooth Parabola Calculation
FIFO
Vertical Serial Data
Vertical E/W Sawtooth
Fig. 2-10: Sync separation block diagram
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2.9. Macrovision Detection Video signals from Macrovision encoded VCR tapes are decoded without loss of picture quality. However, it might be necessary in some applications to detect the presence of Macrovision encoded video signals. This is possible by reading the Macrovision status register (FP-RAM 0x170). Macrovision encoded video signals typically have AGC pulses and pseudo sync pulses added during VBI. The amplitude of the AGC pulses is modulated in time. The Macrovision detection logic measures the VBI lines and compares the signal against thresholds. The window wherein the video lines are checked for Macrovision pulses can be defined in terms of start and stop line (e.g. 6-15 for NTSC).
ADVANCE INFORMATION
2.10.2.Black-Level Expander The black-level expander enhances the contrast of the picture. Therefore the luminance signal is modified with an adjustable, non-linear function. Dark areas of the picture are changed to black, while bright areas remain unchanged. The advantage of this black-level expander is that the black expansion is performed only if it will be most noticeable to the viewer. The black-level expander works adaptively. Depending on the measured amplitudes `Lmin' and `Lmax' of the low-pass-filtered luminance and an adjustable coefficient BTLT, a tilt point `Lt' is established by Lt = Lmin + BTLT (Lmax - Lmin). Above this value there is no expansion, while all luminance values below this point are expanded according to: Lout = Lin + BAM (Lin - Lt)
2.10.Display Processing In the display processing the conversion from digital YCrCb to analog RGB is carried out. A block diagram is shown in Fig. 2-18 on page 24. In the luminance processing path, contrast and brightness adjustments and a variety of features, such as black-level expansion, dynamic peaking and soft limiting, are provided. In the chrominance path, the CrCb signals are converted to 4:4:4 format and filtered by a color transient improvement circuit. The YCrCb signals are converted by a programmable matrix to RGB color space. The display processor provides separate control settings for two pictures, i.e. different coefficients for a `main' and a `side' picture. The digital OSD insertion circuit allows the insertion of a 5-bit OSD signal. The color space for this signal is controlled by a partially programmable color look-up table (CLUT) and contrast adjustment. The OSD signals and the display clock are synchronized to the horizontal flyback. For the display clock, a gate delay phase shifter is used. In the analog backend, three 10-bit digital-to-analog converters provide the analog output signals.
A second threshold, Ltr, can be programmed, above which there is no expansion. The characteristics of the black-level expander are shown in Fig. 2-11and Fig. 2-12.
Lout
Lmax Ltr Lt
BAM BTLT
Lmin
Ltr
BTHR
Lin
Fig. 2-11: Characteristics of the black-level expander
2.10.1.Luma Contrast Adjustment The contrast of the luminance signal can be adjusted by multiplication with a 6-bit contrast value. The contrast value corresponds to a gain factor from 0 to 2, where the value 32 is equivalent to a gain of 1. The contrast can be adjusted separately for main picture and side picture.
The tilt point Lt is a function of the dynamic range of the video signal. Thus, the black-level expansion is only performed when the video signal has a large dynamic range. Otherwise, the expansion to black is zero. This allows the correction of the characteristics of the picture tube.
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VCT 38xxA
a)
Lmax
dB 20 15 10
Lt Lmin
5 0 -5 -10 -15
b)
-20 0 2 4 6 8 10
MHz
Lt
Fig. 2-13: Dynamic peaking frequency response
Fig. 2-12: Black-level expansion a) luminance input b) luminance input and output
2.10.3.Dynamic Peaking Especially with decoded composite signals and notch filter luminance separation, as input signals, it is necessary to improve the luminance frequency characteristics. With transparent, high-bandwidth signals, it is sometimes desirable to soften the image. In the VCT 38xxA, the luma response is improved by `dynamic' peaking. The algorithm has been optimized regarding step and frequency response. It adapts to the amplitude of the high-frequency part. Small AC amplitudes are processed, while large AC amplitudes stay nearly unmodified. The dynamic range can be adjusted from -14 to +14 dB for small high-frequency signals. There is separate adjustment for signal overshoot and for signal undershoot. For large signals, the dynamic range is limited by a non-linear function that does not create any visible alias components. The peaking can be switched over to "softening" by inverting the peaking term by software. The center frequency of the peaking filter is switchable from 2.5 MHz to 3.2 MHz. For S-VHS and for notch filter color decoding, the total system frequency responses for both PAL and NTSC are shown in Fig. 2-14. Transients, produced by the dynamic peaking when switching video source signals, can be suppressed via the priority bus.
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VCT 38xxA
ADVANCE INFORMATION
dB 20 15 10 5 0 -5 -10 -15 -20 0 dB 20 15 10 5 0 -5 -10 -15 -20 0 dB 20 15 10 5 0 -5 -10 -15 -20 0 2 4 6 8 10 MHz 20 2 4 6 8 10 MHz 20 2 4 6 8 10 MHz 20
dB
CF=3.2 MHz
15 10 5
CF=2.5 MHz
S-VHS
0 -5 -10 -15 -20 0 dB 2 4 6 8 10 MHz
CF=3.2 MHz
15 10 5
CF=2.5 MHz
PAL/SECAM
0 -5 -10 -15 -20 0 dB 2 4 6 8 10 MHz
CF=3.2 MHz
15 10 5
CF=2.5 MHz
NTSC
0 -5 -10 -15 -20 0 2 4 6 8 10 MHz
Fig. 2-14: Total frequency response for peaking filter and S-VHS, PAL, NTSC
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VCT 38xxA
Part 1 includes adjustable tilt point and gain. The gain before the tilt value is 1. Above the tilt value, a part (0...15/16) of the input signal is subtracted from the input signal itself. Therefore, the gain is adjustable from 16/16 to 1/16, when the slope value varies from 0 to 15. The tilt value can be adjusted from 0 to 511. Part 2 has the same characteristics as part 1. The subtracting part is also relative to the input signal, so the total differential gain will become negative if the sum of slope 1 and slope 2 is greater than 16 and the input signal is above the both tilt values (see characteristics). Finally, the output signal of the soft limiter will be clipped by a hard limiter adjustable from 256 to 511.
2.10.4.Digital Brightness Adjustment The DC-level of the luminance signal can be adjusted by adding an 8-bit number in the luminance signal path in front of the softlimiter. With a contrast adjustment of 32 (gain+1) the signal can be shifted by 100 %. After the brightness addition, the negative going signals are limited to zero. It is desirable to keep a small positive offset with the signal to prevent undershoots produced by the peaking from being cut. The digital brightness adjustment works separately for main and side picture.
2.10.5.Soft Limiter The dynamic range of the processed luma signal must be limited to prevent the CRT from overload. An appropriate headroom for contrast, peaking and brightness can be adjusted by the TV manufacturer according to the CRT characteristics. All signals above this limit will be `soft'-clipped. A characteristic diagram of the soft limiter is shown in Fig. 2-15. The total limiter consists of three parts:
2.10.6.Chroma Interpolation A linear phase interpolator is used to convert the chroma sampling rate from 10.125 MHz (4:2:2) to 20.25 MHz (4:4:4). All further processing is carried out at the full sampling rate.
Output 511
Part 1 slope 1 [0...15]
Part 2 0 2 4 6 8 10 12 14 slope 2 [0...15]
Hard limiter
400
0 2 4 6 8 10 12 14
Calculation Example for the Softlimiter Input Amplitude. (The real signal processing in the limiter is 2 bit more than described here) Y Input Black Level Contrast Dig. Brightness BLE Peaking 16...235 (ITUR) 16 (constant) 63 20 off off
300
range= 256...511
200
100 tilt 1 [ 0...511] 0 0 100 200 300 400 500 600 700 800 900 tilt 2 [ 0...511]
Limiter input signal: (Yin-Black Level)Contr./32 + Brightn. (235-16) 63/32 + 20 = 451 Limiter Input 1023
Fig. 2-15: Characteristic of soft limiter A and B and hard limiter
2.10.7.Chroma Transient Improvement The intention of this block is to enhance the chroma resolution. A correction signal is calculated by differentiation of the color difference signals. The differentiation can be selected according to the signal bandwidth, e.g. for PAL/NTSC/SECAM or digital component signals, respectively. The amplitude of the correction signal is adjustable. Small noise amplitudes in the correction signal are suppressed by an adjustable coring circuit. To eliminate `wrong colors', which are caused by over and undershoots at the chroma transition, the
sharpened chroma signals are limited to a proper value automatically.
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2.10.9.RGB Processing
a)
ADVANCE INFORMATION
Cr in Cb in
After adding the post-processed luma, the digital RGB signals are limited to 10 bits. Three multipliers are used to digitally adjust the white drive. Using the same multipliers an average beam current limiter is implemented (see Section 2.11.1. on page 25).
t b)
2.10.10.OSD Color Look-up Table The VCT 38xxA has five input lines for an OSD signal. This signal forms a 5-bit address for a color look-up table (CLUT). The CLUT is a memory with 32 words where each word holds a RGB value.
Ampl.
t c)
Bits 0 to 3 (bit 4=0) form the addresses for the ROM part of the OSD, which generates full RGB signals (bit 0 to 2) and half-contrast RGB signals (bit 3). Bit 4 addresses the RAM part of the OSD with 16 freely programmable colors, addressable with bit 0 to 3. The programming is done via the I2C bus.
Cr out Cb out
a) CrCb input of DTI b) CrCb input + correction signal c) sharpened and limited CrCb Fig. 2-16: Digital color transient improvement
t
The amplitude of the CLUT output signals can be adjusted separately for R, G, and B via the I2C bus. The switchover between video RGB and OSD RGB is done via the priority decoder.
2.10.11.Picture Frame Generator When the picture does not fill the total screen (height or width too small) it is surrounded with black areas. These areas (and more) can be colored with the picture frame generator. This is done by switching over the RGB signal from the matrix to the signal from the OSD color look-up table. The width of each area (left, right, upper, lower) can be adjusted separately. The generator starts on the right, respectively lower side of the screen and stops on the left, respectively upper side of the screen. This means, it runs during horizontal, respectively vertical flyback. The color of the complete border can be stored in the programmable OSD color look-up table in a separate address. The format is 3 x 4-bit RGB. The contrast can be adjusted separately. The picture frame generator includes a priority master circuit. Its priority is programmable and the border is generated only if the priority is higher than the priority of the other sources (video/OSD). Therefore, the border can be underlay or overlay depending on the picture source.
2.10.8.Inverse Matrix A 6-multiplier matrix transcodes the Cr and Cb signals to R-Y, B-Y, and G-Y. The multipliers are also used to adjust color saturation in the range of 0 to 2. The coefficients are signed and have a resolution of 9 bits. There are separate matrix coefficients for main and side pictures. The matrix computes: R-Y= MR1*Cb+MR2*Cr G-Y= MG1*Cb+MR2*Cr B-Y= MB1*Cb+MR2*Cr The initialization values for the matrix are computed from the standard ITUR (CCIR) matrix:
R G B
=
1 1 1
0 -0.345 1.773
1.402 -0.713 0
Y Cb Cr
For a contrast setting of CTM+32, the matrix values are scaled by a factor of 64 (see Table 2-4 on page 34).
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VCT 38xxA
2.10.13.Scan Velocity Modulation The RGB input signal of the SVM is converted to Y in a simple matrix. Then the Y signal is differentiated by a filter of the transfer function 1-Z-N, where N is programmable from 1 to 6. With a coring, some noise can be suppressed. This is followed by a gain adjustment and an adjustable limiter. The analog output signal is generated by an 8-bit D/A converter. The signal delay can be adjusted by 3.5 clocks in half-clock steps. For the gain and filter adjustment there are two parameter sets. The switching between these two sets is done with the same RGB switch signal that is used for switching between video-RGB and OSD-RGB for the RGB outputs (see Fig. 2-17).
2.10.12.Priority Decoder The priority decoder selects the picture source depending on the programmed priorities. Up to eight levels can be selected for OSD and the picture frame - where 0 is the highest. The video source always has the lowest priority. A 5-bit information is attached to each priority (see Table 2-4 on page 34). These bits are programmable via the I2C bus and have the following meanings: - one of two contrast, brightness and matrix values for main and side picture - RGB from video signal or color look-up table - disable/enable black-level expander - disable/enable peaking transient suppression when signal is switched - disable/enable analog Fast-Blank input
R
G
B
RGB Switch N1 N2 Coring Gain1 Gain2 Limit Delay
Matrix and Shaping Modulation Notch
Differentiator 1-Z-Nx
Coring adjustment
Gain adjustment
Limiter
Delay adjustment
D/A Converter
Output
Fig. 2-17: SVM Block diagram
2.10.14.Display Phase Shifter A phase shifter is used to partially compensate the phase differences between the video source and the flyback signal. By using the described clock system, this phase shifter works with an accuracy of approximately 1 ns. It has a range of 1 clock period which is equivalent to 24.7 ns at 20.25 MHz. The large amount of phase shift (full clock periods) is realized in the front-end circuit.
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Fig. 2-18: Digital back-end
dig. Y in
8 5
VCT 38xxA
Contrast
Brightness + Offset
White-Drive Measurement
Dynamic peaking
CLOCK
prio
Softlimiter
luma insert for CRTmeasurement
Picture Frame Generator
White-Drive R x beam Curr. Lim.
Display
& Clock Control
Horizontal Flyback
CLUT, Contrast
dig. OSD in BlackLevel Expander
8 Blanking for CRT Measurement
Y Matrix R'
Phase Shift 0...1 Clock R
White-Drive G x Beam curr. Lim.
dig. Rout
10
prio
Cr
dig. CrCb in
DTI (Cr)
Interpol 4:4:4
Matrix G' DTI (Cb)
Phase Shift 0...1 Clock G
White-Drive x Beam Curr. Lim.
dig. Gout
10
Cb
PRIO in
3
Side Picture
PRIO Decoder
select Coefficients
Main Picture
Matrix B'
Phase Shift 0...1 Clock B
dig. Bout
10
ADVANCE INFORMATION
Scan Velocity Modulation
Matrix Saturation
SVMout
ADVANCE INFORMATION
VCT 38xxA
Cutoff and white-drive current measurement are carried out during the vertical blanking interval. They always use the small bandwidth setting. The current range for the cutoff measurement is set by connecting a sense resistor to the MADC input. For the white-drive measurement, the range is set by using another sense resistor and the range select switch 2 output pin (RSW2). During the active picture, the minimum and maximum beam current is measured. The measurement range can be set by using the range select switch 1 pin (RSW1) as shown in Fig. 2-19 and Fig. 2- 20. The timing window of this measurement is programmable. The intention is, to automatically detect letterbox transmission or to measure the actual beam current. All control loops are closed via the external control microprocessor.
2.11.Video Back-end The digital RGB signals are converted to analog RGBs using three video digital-to-analog converters (DAC) with 10-bit resolution. An analog brightness value is provided by three additional DACs. The adjustment range is 40 % of the full RGB range. Controlling the white-drive/analog brightness and also the external contrast and brightness adjustments is done via the Fast Processor, located in the front-end. Control of the cutoff DACs is done via I2C bus registers. Finally cutoff and blanking values are added to the RGB signals. Cutoff (dark current) is provided by three 9-bit DACs. The adjustment range is 60 % of full scale RGB range. The analog RGB-outputs are current outputs with current-sink characteristics. The maximum current drawn by the output stage is obtained with peak white RGB. An external half contrast signal can be used to reduce the output current of the RGB outputs to 50 %.
Beam Current A D MADC
SENSE
RSW1
R2 R3
2.11.1.CRT Measurement and Control
RSW2
The display processor is equipped with an 8-bit PDM-ADC for all measuring purposes. The ADC is connected to the SENSE input pin, the input range is 0 to 1.5V. The bandwidth of the PDM filter can be selected; it is 40/80 kHz for small/large bandwidth setting. The input impedance is more than 1 M. Fig. 2-19: MADC range switches
R1
CR + IBRM + WDRVWDR CR + IBRM white drive R
black ultra black
CG + IBRM
cutoff R
R
cutoff G
G
cutoff B
CB + IBRM
B
active measurement resistor
R1||R2||R3 RSW1=on, RSW2=on PICTURE MEAS.
R1
R1||R3 RSW2 =on
R1||R2||R3 RSW1=on, RSW2=on PICTURE MEAS. PMST
TUBE MEASUREMENT TML
Lines
PMSO
Fig. 2-20: MADC measurement timing
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In each field two sets of measurements can be taken: a) The picture tube measurement returns results for - cutoff R - cutoff G - cutoff B - white-drive R or G or B (sequentially) b) The picture measurement returns data on - active picture maximum current - active picture minimum current
active video field 1/ 2
ADVANCE INFORMATION
tube measurement picture meas. start
picture meas. end
small window for tube measurement (cutoff, white drive)
large window for active picture
The tube measurement is automatically started when the cutoff blue result register is read. Cutoff control for RGB requires one field only, whereas a complete white-drive control requires three fields. If the measurement mode is set to `offset check', a measurement cycle is run with the cutoff/white-drive signals set to zero. This allows to compensate the MADC offset as well as input the leakage currents. During cutoff and white-drive measurements, the average beam current limiter function (see Section 2.11.3. on page 27) is switched off and a programmable value is used for the brightness setting. The start line of the tube measurement can be programmed via I2C bus, the first line used for the measurement, i.e. measurement of cutoff red, is 2 lines after the programmed start line. The picture measurement must be enabled by the control microprocessor after reading the min./max. result registers. If a `1' is written into bit 2 in subaddress 25, the measurement runs for one field. For the next measurement a `1' has to be written again. The measurement is always started at the beginning of active video. The vertical timing for the picture measurement is programmable, and may even be a single line. Also the signal bandwidth is switchable for the picture measurement. Two horizontal windows are available for the picture measurement. The large window is active for the entire active line. Tube measurement is always carried out with the small window. Measurement windows for picture and tube measurement are shown in Fig. 2-21.
picture meas. start
Fig. 2-21: Windows for tube and picture measurements
2.11.2.SCART Output Signal The RGB output of the VCT 38xxA can also be used to drive a SCART output. In the case of the SCART signal, the parameter CLMPR (clamping reference) has to be set to 1. Then, during blanking, the RGB outputs are automatically set to 50 % of the maximum brightness. The DC offset values can be adjusted with the cutoff parameters CR, CG, and CB. The amplitudes can be adjusted with the drive parameters WDR, WDG, and WDB.
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VCT 38xxA
2.11.4.Analog RGB Insertion The VCT 38xxA allows insertion of external analog RGB signals. The RGB signal is key-clamped and inserted into the main RGB by the Fast-Blank switch. The external RGB input can be overlaid or underlaid to the digital picture. The external RGB signals can be adjusted independently as regards DC level (brightness) and magnitude (contrast). All signals for analog RGB insertion (RIN, GIN, BIN, FBLIN) must be synchronized to the horizontal flyback, otherwise a horizontal jitter will be visible. The VCT 38xxA has no means for timing correction of the analog RGB input signals.
2.11.3.Average Beam Current Limiter The average beam current limiter (BCL) uses the SENSE input for the beam current measurement. The BCL uses a different filter to average the beam current during the active picture. The filter bandwidth is approx. 2 kHz. The beam current limiter has an automatic offset adjustment that is active two lines before the first cutoff measurement line. The beam current limiter function is located in the front-end. The data exchange between the front-end and the back-end is done via a single-wire serial interface. The beam current limiter allows the setting of a threshold current. If the beam current is above the threshold, the excess current is low-pass filtered and used to attenuate the RGB outputs by adjusting the white-drive multipliers for the internal (digital) RGB signals, and the analog contrast multipliers for the analog RGB inputs, respectively. The lower limit of the attenuator is programmable, thus a minimum contrast can always be set. During the tube measurement, the ABL attenuation is switched off. After the white-drive measurement line it takes 3 lines to switch back to BCL limited drives and brightness. Typical characteristics of the ABL for different loop gains are shown in Fig. 2-22; for this example the tube has been assumed to have square law characteristics.
2.11.5.Fast-Blank Monitor The presence of external analog RGB sources can be detected by means of a Fast-Blank monitor. The status of the Fast-Blank input can be monitored via an I2C bus register. There is a 2 bit information, giving static and dynamic indication of a Fast-Blank signal. The static bit is directly reading the Fast-Blank input line, whereas the dynamic bit is reading the status of a flip-flop triggered by the negative edge of the FastBlank signal. With this monitor logic it is possible to detect if there is an external RGB source active and if it is a full screen insertion or only a box. The monitor logic is connected directly to the FBLIN pin.
Fig. 2-22: Beam current limiter characteristics: beam current output vs. drive BCL threshold: 1
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ADVANCE INFORMATION
digital SVM in 8
8-bit DAC SVM 1.88 mA 0.94 mA
int. brightness * white drive R
analog SVM out
9-bit DAC 1.5 mA 9-bit DAC 2.2 mA
cutoff R
digital R in 10
10-bit DAC Video 3.75 mA
int. brightness * white drive G
blanking 750 A analog R out
9-bit DAC 1.5 mA 9 bit DAC 2.2 mA
cutoff G
digital G in 10
10-bit DAC Video 3.75 mA
int. brightness * white drive B
blanking 750 A analog G out
9-bit DAC 1.5 mA
cutoff B
digital B in 10
10-bit DAC Video 3.75 mA
9 bit DAC 2.2 mA
blanking 750 A analog B out
H
ext. brightness * white drive R ext. brightness * white drive G ext. brightness * white drive B
V
serial interface
9-bit DAC 1.5 mA
9-bit DAC 1.5 mA
9-bit DAC 1.5 mA
blank & measurem. timing
white drive R white drive G
ext. contrast * white drive G * beam current lim.
ext. contrast * white drive R * beam current lim.
white drive B int . brightness ext. contrast ext. brightness
9-bit U/I-DAC 3.75 mA clamp
9-bit U/I-DAC 3.75 mA clamp
ext. contrast * white drive B * beam current lim.
9-bit U/I-DAC 3.75 mA clamp
8 bit ADC measurm.
key
analog
R in
analog G in
analog B in
fast blank in
SENSE Input
Fig. 2-23: Video back-end
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measurement buffer
I/O
ADVANCE INFORMATION
VCT 38xxA
2.12.3.Horizontal Phase Adjustment This section describes a simple way to align PLL phases and the horizontal frame position. 1. With HDRV the duration of the horizontal drive pulse has to be adjusted 2. With POFS2 the delay between input video and display timing (e.g. clamping pulse for analog RGB) has to be adjusted 3. With CSYDEL the delay between video and analog RGB (OSD) has to be adjusted. 4. With CSYDEL and HPOS the horizontal position of both, the digital and analog RGB signal (from SCART) relative to the clamping pulse has to be adjusted to the correct position, e.g. the pedestal of the generator signal. 5. With POFS3 the position of horizontal drive/flyback relative to RGB has to be adjusted 6. With NEWLIN the position of a scaled video picture can be adjusted (left, middle, center, etc; versions with panorama scaler only). 7. With HBST and HBSO, the start and stop values for the horizontal blanking have to be adjusted. Note: The processing delay of the internal digital video path differs depending on the comb filter option of the VCT 38xxA. The versions with comb filter have an additional delay of 34 clock cycles.
2.12.Synchronization and Deflection The synchronization and deflection processing is distributed over front-end and back-end. The video clamping, horizontal and vertical sync separation and all video related timing information are processed in the front-end. Most of the processing that runs at the horizontal frequency is programmed on the internal Fast Processor (FP). Also the values for vertical and East/West deflection are calculated by the FP software. The generation of horizontal and vertical drive signals can be synchronized to the video timing extracted in the front-end or to a free running line counter in the back-end.
2.12.1.Deflection Processing The deflection processing generates the signals for the horizontal and vertical drive (see Fig. 2-24). This block contains two phase-locked loops: - PLL2 generates the horizontal and vertical timing, e.g. blanking, clamping and composite sync. Phase and frequency are synchronized by the front sync signal. - PLL3 adjusts the phase of the horizontal drive pulse and compensates for the delay of the horizontal output stage. Phase and frequency are synchronized by the oscillator signal of PLL2. The horizontal drive circuitry uses a digital sine wave generator to produce the exact (subclock) timing for the drive pulse HOUT. The generator runs at 1 MHz. Under control of the EHPLL bit and the internal voltage supervision it is either synchronized by the deflection PLL or it is free running. In the output stage the frequency is divided down to give drive-pulse period and width. The drive pulse width is programmable. The horizontal drive uses an open drain output transistor. After power on or during reset the HOUT generation is switched to a free running mode with a fix duty cycle of 50 %. For normal operation the EHPLL bit has to be set first. During the switch the actual period of HOUT can vary by up to 1 s.
2.12.2.Angle and Bow Correction The Angle and Bow correction is part of the horizontal drive PLL. This feature allows a shift of the horizontal drive pulse phase depending on the vertical position on the screen. The phase correction has a linear (angle) and a quadratic term (bow).
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VCT 38xxA
ADVANCE INFORMATION
HFLB
PLL3
Skew Measurement Phase Comparator & Low-pass DCO Sinewave DAC Generator & LPF 1:64 & Output Stage HOUT
+
Angle & Bow
blanking, clamping, etc.
MSY
Main Sync Generator Front Sync Interface
Display Timing Phase Comparator & Low-pass
PLL2
Sync Generation DCO Line Counter INTLC
FSY
vertical reset
Clock & Control
VPROT
E/W correction VDATA Vertical Data Sawtooth
PWM 15-bit
EW
PWM 15-bit
VERT VERTQ
Fig. 2-24: Deflection processing block diagram
2.12.4.Vertical and East/West Deflection The calculations of the vertical and East/West deflection waveforms is done by the internal Fast Processor (FP). The algorithm uses a chain of accumulators to generate the required polynomial waveforms. To produce the deflection waveforms, the accumulators are initialized at the beginning of each field. The initialization values must be computed by the TV control processor and are written to the front-end once. The waveforms are described as polynomials in x, where x varies from 0 to 1 for one field. P: a + b(x-0.5) + c(x-0.5)2 + d(x-0.5)3 + e(x-0.5)4 The initialization values for the accumulators a0..a3 for vertical deflection and a0..a4 for East/West deflection are 12-bit values. Fig. 2-25 shows several vertical and East/West deflection waveforms. The polynomial coefficients are also stated.
In order to get a faster vertical retrace timing, the output impedance of the vertical D/A-converter can be reduced by 50 % during the retrace.
2.12.5.EHT Compensation The vertical waveform can be scaled according to the average beam current. This is used to compensate the effects of electric high-tension changes due to beam current variations. EHT compensation for East/West deflection is done with an offset corresponding to the average beam current.
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Micronas
ADVANCE INFORMATION
VCT 38xxA
2.12.6.Protection Circuitry Picture tube and drive stage protection is provided through the following measures: - Vertical flyback protection input: This pin searches for a negative edge in every field, otherwise the RGB drive signals are blanked. - Drive shutoff during flyback: This feature can be selected by software. - Safety input pin: This input has two thresholds. Between zero and the lower threshold, normal functioning takes place. Between the lower and the higher threshold, the RGB signals are blanked. Above the higher threshold, the RGB signals are blanked and the horizontal drive is shut off. Both thresholds have a small hysteresis.
Vertical:
a,b,c,d 0,1,0,0 0,1,1,0 0,1,0,1
East/West:
a,b,c,d,e 0,0,1,0,0 0,0,0,0,1 0,0,1,1,1
Fig. 2-25: Vertical and East/West deflection waveforms
2.13.Reset Function Reset of all VDP functions is performed by the RESQ pin. When this pin becomes active, all internal registers and counters are lost. The TV controller can activate the RESQ pin by software (see Section 5.7.2. on page 90). When the RESQ pin is released, the internal reset is still active for 4 s. After that time, the initialization of all required registers is performed by the internal Fast Processor. This takes approximately 60 s. During this initialization procedure it is not possible to access the VDP via the I2C interface. The VDP has clock and voltage supervision circuits to generate a stable HOUT signal. The voltage supervision activates an internal reset signal when the supply
for the digital circuits (VSUPD) goes below ~2.5 V for more than 50 ns. This reset signal is extended by 50 s after VSUPD is back again. 2.14.Standby and Power-On The VDP does not have a standby mode. To disable all the analog and digital video functions, it is necessary to switch off the supplies for analog front-end (VSUPAF), analog back-end (VSUPAB) and digital circuitry (VSUPD).
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VCT 38xxA
2.15.I2C Bus Slave Interface Communication between the VDP and the TV controller is done via I2C bus. For detailed information on the I2C bus please refer to the Philips manual `I2C bus Specification'. The VDP has two I2C bus slave interfaces (for compatibility with VPC/DDP applications) - one in the front-end and one in the back-end. Both I2C bus interfaces use I2C clock synchronization to slow down the interface if required. Both I2C bus interfaces use one level of subaddress: the I2C bus chip address is used to address the VDP and a subaddress selects one of the internal registers. The I2C bus chip addresses are given below: Table 2-2: I2C chip addresses
Chip Address front-end back-end A6 A5 A4 A3 A2 A1 A0 R/W
ADVANCE INFORMATION
Fig. 2-26 shows I2C bus protocols for read and write operations of the interface; the read operation requires an extra start condition and repetition of the chip address with read command set.
2.15.1.Control and Status Registers Table 2-3 gives definitions of the VDP control and status registers. The number of bits indicated for each register in the table is the number of bits implemented in hardware, i.e. a 9-bit register must always be accessed using two data bytes but the 7 MSB will be `don't care' on write operations and `0' on read operations. Write registers that can be read back are indicated in Table 2-3. Functions implemented by software in the on-chip control microprocessor (FP) are explained in Table 2-5. A hardware reset initializes all control registers to 0. The automatic chip initialization loads a selected set of registers with the default values given in Table 2-3. The register modes given in Table 2-3 are - w: - w/r: write only register write/read data register read data from VDP register is latched with vertical sync register is latched with horizontal
1 1
0 0
0 0
0 0
1 1
1 0
1 1
1/0 1/0
The registers of the VDP have 8 or 16-bit data size; 16-bit registers are accessed by reading/writing two 8-bit data words.
- r: - v: - h:
S
1000 111
W Ack
0111 1100
Ack 1 or 2 byte Data
P
I2C write access subaddress 7c
high byte Data Ack low byte Data Nak P
S
1000 111
W Ack
0111 1100
Ack S
1000 111
R
I2C read access subaddress 7c
SDA
1 0 S P
SCL
W R Ack Nak S P
= = = = = =
0 1 0 1 Start Stop
Fig. 2-26: I2C bus protocols
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ADVANCE INFORMATION
VCT 38xxA
Table 2-3: I2C control and status registers of the video front-end
I2C Sub address
Number of bits
Mode
Function
Default
Name
FP Interface h'35 8 r FP status bit [0] bit [1] bit [2] bit[8:0] bit[11:9] bit[8:0] bit[11:9] bit[11:0] FPSTA write request read request busy 9-bit FP read address reserved, set to zero 9-bit FP write address reserved, set to zero FP data register, reading/writing to this register will autoincrement the FP read/ write address. Only 16 bit of data are transferred per I2C telegram. Black Line Detector h'12 16 r read only register, do not write to this register! after reading, LOWLIN and UPLIN are reset to 127 to start a new measurement bit[6:0] number of lower black lines bit[7] always 0 bit[14:8] number of upper black lines bit[15] normal/black picture Miscellaneous h'29 16 w/r Test pattern generator: bit[10:0] reserved (set to 0) bit[11] 0/1 disable/enable test pattern generator bit[13:12] output mode: 00 Y/C = ramp (240 ... 17) 01 Y/C = 16 10 Y/C = 90 11 Y/C = 240 bit[15:14] 0/1 reserved (set to 0) NEWLINE (available for versions with panorama scaler only): bit[10:0] NEWLINE register This register defines the readout start of the next line in respect to the value of the sync counter. bit [15:11] reserved (set to 0) TPG 0 0 0
TPGEN TPGMODE
h'36 h'37 h'38
16 16 16
w w w/r
FPRD FPWR FPDAT
BLKLIN
LOWLIN UPLIN BLKPIC
0 NEWLIN 0
h'22
16
w/r
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VCT 38xxA
Table 2-4: I2C control and status registers of the video back-end
ADVANCE INFORMATION
I2C Sub address
Number of bits
Mode
Function 1)
Default
Name
priority mask register If bit[x] is set to 1 then the function is active for the respective signal priority Luminance Channel h'61 h'65 h'51 h'55 h'75 9 9 9 9 9 wv wv wv wv wv bit [5:0] bit [5:0] bit [8:0] bit [8:0] 0..63/32 0..63/32 main picture contrast side picture contrast main picture brightness side picture brightness 32 CTM 32 CTS 0 BRM 0 BRS 0 PBCT 1)
-256..255 -256..255
luma channel, priority mask register bit [7:0] 0/1 select contrast, brightness, matrix for main/side picture luma channel, priority mask register bit [7:0] 0/1 select main (video) / external (via CLUT) RGB Black-Level Expander
h'71
9
wv
0 PBERGB 1)
h'59
9
wv
black-level expander bit [3:0] 0..15 bit [8:4] 0...31
tilt coefficient amount
BLE1 8 BTLT 12 BAM BLE2 200 BTHR BLE3 0 BWL 15 BVST
h'5d h'73
9 9
wv wv
black-level expander, threshold: bit [8:0] 0..511 disable expansion, threshold value black-level expander, measurement bit[0] 0/1 50/60 Hz measurement windowlength bit [8:1] 0..255 vstart/2 start line = vstart stop line = 336/283 - vstart or vertical blanking black-level expander, priority mask register bit [7:0] 0/1 enable/disable black-level expander Dynamic Peaking
h'7d
9
wv
0 PBBLE 1)
h'69
9
wv
luma peaking filter, the gain at high frequencies and small signal amplitudes is: 1 + (k1+k2)/8 bit [3:0] 0..15 k1: peaking level undershoot bit [7:4] 0..15 k2: peaking level overshoot bit [8] 0/1 peaking value normal/inverted (peaking/softening) luma peaking filter, coring bit [4:0] 0..31 coring level bit [7:5] reserved bit [8] 0/1 peaking filter center frequency high/ low luma peaking filter, priority mask register bit [7:0] 0/1 disable/enable peaking transient suppression when signal is switched
PK1 4 PKUN 4 PKOV 0 PKINV PK2 3 COR 0 PFS 0 PBPK 1)
h'6d
9
wv
h'79
9
wv
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Micronas
ADVANCE INFORMATION
VCT 38xxA
I2C Sub address
Number of bits
Mode
Function
Default
Name
Soft Limiter h'41 9 wv luma soft limiter, slope A and B bit [3:0] slope segment A bit [7:4] slope segment B luma soft limiter, absolute limit bit [7:0] luma soft limiter absolute limit (unsigned) bit [8] 0/1 modulation off/on bit [8:0] bit [8:0] luma soft limiter segment B tilt point (unsigned) luma soft limiter segment A tilt point (unsigned) Chrominance Channel h'14 8 w/r luma/chroma matching bit [2:0] -3...3 variable chroma delay bit [7:3] reserved, set to 0 digital transient improvement bit [3:0] 0..15 coring value bit [7:4] 0..15 DTI gain bit [8] 0/1 narrow/wide bandwidth mode Inverse Matrix h'7c h'74 h'6c h'64 h'5c h'54 h'78 h'70 h'68 h'60 h'58 h'50 9 9 9 9 9 9 9 9 9 9 9 9 wv wv wv wv wv wv wv wv wv wv wv wv main picture matrix coefficient R-Y = MR1M*CB + MR2M*CR bit [8:0] -256/128 ... 255/128 -256/128 ... 255/128 bit [8:0] main picture matrix coefficient G-Y = MG1M*CB + MG2M*CR bit [8:0] -256/128 ... 255/128 -256/128 ... 255/128 bit [8:0] main picture matrix coefficient B-Y = MB1M*CB + MB2M*CR bit [8:0] -256/128 ... 255/128 -256/128 ... 255/128 bit [8:0] side picture matrix coefficient R-Y = MR1S*CB + MR2S*CR bit [8:0] -256/128 ... 255/128 -256/128 ... 255/128 bit [8:0] side picture matrix coefficient G-Y = MG1S*CB + MG2S*CR bit [8:0] -256/128 ... 255/128 -256/128 ... 255/128 bit [8:0] side picture matrix coefficient B-Y = MB1S*CB + MB2S*CR bit [8:0] -256/128 ... 255/128 -256/128 ... 255/128 bit [8:0] 0 MR1M, 86 MR2M LCM 0 CDEL DTI 1 DTICO 5 DTIGA 1 DTIMO LSL1 0 LSLSA 0 LSLSB LSL2 255 LSLAL 1 LSLM 300 LSLTB 250 LSLTA
h'45
9
wv
h'49 h'4d
9 9
wv wv
h'5e
9
wv
-22 MG1M, -44 MG2M
113 MB1M, 0 MB2M 0 MR1S, 73 MR2S
-19 MG1S, -37 MG2S
97 MB1S, 0 MB2S
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VCT 38xxA
ADVANCE INFORMATION
I2C Sub address
Number of bits
Mode
Function
Default
Name
Color Lookup Table h'00- h'0f 16 wh color look-up table : 16 entries, 12 bit wide, The CLUT registers are initialized at power-up bit [3:0] 0..15 blue amplitude bit [7:4] 0..15 green amplitude bit [11:8] 0..15 red amplitude 000h CLUT0 f00h 0f0h ff0h 00fh f0fh 0ffh fffh 7ffh 700h 070h 770h 007h 707h 077h 777h CLUT15 RCT 8 DRCT
h'4c
9
wv
digital OSD insertion contrast for R (amplitude range: 0 to 255) bit [3:0] 0..13 R amplitude = CLUTn (DRCT + 4) 14,15 invalid picture frame insertion contrast for R (ampl. range: 0 to 255) bit [7:4] 0..13 R amplitude = PFCR (PFRCT + 4) 14,15 invalid digital OSD insertion contrast for G (amplitude range: 0 to 255) bit [3:0] 0..13 G amplitude = CLUTn (DGCT + 4) 14,15 invalid picture frame insertion contrast for G (ampl. range: 0 to 255) bit [7:4] 0..13 G amplitude = PFCG (PFGCT + 4) 14,15 invalid digital OSD insertion contrast for B (amplitude range: 0 to 255) bit [3:0] 0..13 B amplitude = CLUTn (DBCT + 4) 14,15 invalid picture frame insertion contrast for B (ampl. range: 0 to 255) bit [7:4] 0..13 B amplitude = PFCB (PFBCT + 4) 14,15 invalid Picture Frame Generator
8 PFRCT GCT 8 DGCT
h'48
9
wv
8 PFGCT BCT 8 DBCT
h'44
9
wv
8 PFBCT
h'11
16
wh
picture frame color bit [3:0] 0..15 bit [7:4] 0..15 bit [11:8] 0..15 bit [2:0] bit [8]
blue amplitude green amplitude red amplitude
PFC 0 PFCB 0 PFCG 0 PFCR 0 PFGID PFGEN 0 PFGHB
h'47 h'4F
9 9
wv wv
picture frame generator priority id enable prio id for picture frame generator
bit [8:0] horizontal picture frame begin code 0 = picture frame generator horizontally disabled code 1FF = full frame bit [8:0] horizontal picture frame end bit [8:0] vertical picture frame begin code 0 = picture frame generator vertically disabled bit [8:0] vertical picture frame end
h'53 h'63 h'6f
9 9 9
wv wv wv
0 PFGHE 270 PFGVB 56 PFGVE
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Micronas
ADVANCE INFORMATION
VCT 38xxA
I2C Sub address
Number of bits
Mode
Function
Default
Name
Scan Velocity Modulation h'5a 9 wv video mode coefficients bit [5:0] gain1 bit [8:6] differentiator delay 1 (0= filter off, 1...6= delay) text mode coefficients bit [5:0] gain 2 bit [8:6] differentiator delay 2 (0= filter off, 1...6= delay) limiter bit [6:0] bit [8:5] limit value not used, set to "0" SVM1 60 SVG1 4 SVD1 SVM2 60 SVG2 4 SVD2 SVM3 100 SVLIM 0 SVM4 7 SVDEL
h'56
9
wv
h'52
9
wv
h'4e
9
wv
delay and coring bit [3:0] adjustable delay, in 1/2 display clock steps, (value 5 : delay of SVMOUT is the same as for RGBOUT bit [7:4] coring value bit [8] not used, set to "0" Display Controls
0 SVCOR
h'4a h'46 h'42
9 9 9
wv wv wv
cutoff Red cutoff Green cutoff Blue Tube- and Picture-Measurements
0 CR 0 CG 0 CB
h'7b h'6b h'7f h'25
9 9 9 8
wv wv wv w/r
picture measurement start line bit [8:0] (TML+9)..511 first line of picture measurement picture measurement stop line bit [8:0] (PMST+1)..511 last line of picture measurement tube measurement line bit [8:0] 0..511 start line for tube measurement tube and picture measurement control bit [0] 0/1 disable/enable tube measurement bit [1] 0/1 80/40 kHz bandwidth for picture measurement bit [2] 0/1 disable/enable picture measurement (writing a '1' starts one measurement cycle) bit [3] 0/1 large/small picture measurement window, will be disabled from bit[3] in address h'32 bit [4] 0/1 measure / offset check for adc bit [7:5] reserved white drive measurement control bit [9:0] 0..1023 RGB values for white drive beam current measurement bit [10] reserved bit [11] 0/1 RGB values for white drive beam current measurement disabled/enabled
PMST 23 PMSO 308 TML 15 0 TPM TMEN PMBW PMEN
PMWIN OFSEN WDM 512 WDRV
h'13
16
w/r
0 EWDM
Micronas
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VCT 38xxA
ADVANCE INFORMATION
I2C Sub address
Number of bits
Mode
Function
Default
Name
8 h'18 h'19 h'1a h'1d h'1c h'1b h'1e 8
r
measurement result registers minimum in active picture maximum in active picture white drive cutoff/leakage red cutoff/leakage green cutoff/leakage blue, read pulse starts tube measurement measurement adc status and Fast-Blank input status measurement status register bit [0] 0/1 tube measurement active / complete bit [2:1] white drive measurement cycle 00 red 01 green 10 blue 11 reserved bit [3] 0/1 picture measurement active / complete bit [4] 0/1 Fast-Blank input Low / High (static) bit [5] 1 Fast-Blank input negative transition since last read (bit reset at read) bit [7:6] reserved Vertical Timing
-
MRMIN MRMAX MRWDR MRCR MRCG MRCB
r
- PMS
h'67 h'77 h'5f
9 9 9
wv wv wv
vertical blanking start bit [8:0] 0..511 first line of vertical blanking vertical blanking stop bit [8:0] 0..511 last line of vertical blanking vertical free run period bit [8:0] free running field period = (value+4) lines Horizontal Deflection and Timing
VBST 305 VBSO 25 VPER 309
h'7a h'76 h'6e
9 9 9
wv wv wv
quadratic term of angle & bow correction bit [8:0] -256..+255 ( 500 ns) linear term of angle & bow correction bit [8:0] -256..+255 ( 500 ns) adjustable delay of PLL2, clamping, and blanking (relative to front sync) adjust clamping pulse for analog RGB input bit [8:0] -256..+255 ( 8 s) adjustable delay of flyback, main sync, csync and analog RGB (relative to PLL2) adjust horizontal drive or csync -256..+255 ( 8 s) bit [8:0] adjustable delay of main sync (relative to flyback) adjust horizontal position for digital picture bit [8:0] 20 steps=1 s start of horizontal blanking bit [8:0] 0..511
0 BOW 0 ANGLE
-141 POFS2
h'72
9
wv
0 POFS3
h'7e
9
wv
120 HPOS
h'5b
9
wv
1 HBST
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Micronas
ADVANCE INFORMATION
VCT 38xxA
I2C Sub address
Number of bits
Mode
Function
Default
Name
h'57
9
wv
end of horizontal blanking bit [8:0] 0..511 PLL2/3 filter coefficients, 1of5 bit code (n+ set bit number) bit [5:0] proportional coefficient PLL3, 2-n-1 bit [5:0] proportional coefficient PLL2, 2-n-1 bit [5:0] integral coefficient PLL2, 2-n-5 horizontal drive and vertical signal control register bit [5:0] 0..63 horizontal drive pulse duration in s (internally limited to 4..61) bit [6] 0/1 disable/enable horizontal PLL2 and PLL3 bit [7] 0/1 1: disable horizontal drive pulse during flyback bit [8] reserved, set to '0' bit [9] 0/1 enable/disable ultra black blanking bit [10] 0/1 0: all outputs blanked 1: normal mode bit [11] 0/1 enable/disable clamping for analog RGB input bit [12] 0/1 disable/enable vertical free running mode (FIELD is set to field2, no interlace) bit [13] 0/1 enable/disable vertical protection bit [14] reserved, set to '0' bit [15] 0/1 disable/enable phase shift of display clock sync output control bit [0] invert INTLC bit [4:1] reserved, set to '0' bit [5] force INTLC to polarity defined in `INTLCINV' Miscellaneous
48 HBSO
h'62 h'66 h'6a h'15
9 9 9 16
wv wv wv w/r
2 PKP3 1 PKP2 2 PKI2 HVC 32 HDRV 0 EHPLL 0 EFLB 0 0 DUBL 1 EBL 0 DCRGB 0 SELFT 0 DVPR 0 1 DISKA 0 SYCTRL INTLCINV INTLCFO
h'9d
8
w/r
h'32
8
w/r
Fast-Blank interface mode bit [0] 0 internal Fast-Blank from FBLIN pin 1 force internal Fast-Blank signal to High bit [1] 0/1 internal Fast-Blank active High/Low bit [2] 0/1 disable/enable clamping reference for RGB outputs bit [3] 1 full line MADC measurement window, disables bit [3] in address h'25 bit [4] 0/1 horizontal flyback input active High/Low bit [6:5] reserved (set to 0) bit [7] vertical output select 0 VERTQ output 1 INTLC output Fast-Blank input, priority mask register bit [7:0] 0/1 disable/enable analog Fast-Blank input
0 FBMOD FBFOH FBPOL CLMPR FLMW FLPOL VOS
h'4b
9
wv
0 PBFB 1)
Micronas
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VCT 38xxA
ADVANCE INFORMATION
Table 2-5: Control registers of the Fast Processor for control of the video front-end functions
- default values are initializied at reset
FP Subaddress
Function
Default
Name
Standard Selection h'20 Standard select: bit[2:0] standard 0 PAL B,G,H,I (50 Hz) 4.433618 1 NTSC M (60 Hz) 3.579545 2 SECAM (50 Hz) 4.286 3 NTSC44 (60 Hz) 4.433618 4 PAL M (60 Hz) 3.575611 5 PAL N (50 Hz) 3.582056 6 PAL 60 (60 Hz) 4.433618 7 NTSC COMB (60 Hz) 3.579545 bit[3] 0/1 standard modifier PAL modified to simple PAL NTSC modified to compensated NTSC SECAM modified to monochrome 625 NTSCC modified to monochrome 525 bit[4] reserved (set to 0) bit[5] 0/1 2-H comb filter off/on bit[6] 0/1 S-VHS mode off/on (2-H comb is switched off) Option bits allow to suppress parts of the initialization, this can be used for color standard search: bit[7] bit[8] bit[9] bit[10] bit[11] no hpll setup no vertical setup no acc setup 2-H comb filter set-up only status bit, normally write 0. After the FP has switched to a new standard, this bit is set to 1 to indicate operation complete. Standard is automatically initialized when the insel register is written. 0 ASR_ENA 0 SDT PAL NTSC SECAM NTSC44 PALM PALN PAL60 NTSCC SDTMOD
COMB SVHS SDTOPT
h'148
Enable automatic standard recognition (ASR) bit[0] 0/1 PAL B,G,H,I (50 Hz) 4.433618 bit[1] 0/1 NTSC M (60 Hz) 3.579545 bit[2] 0/1 SECAM (50 Hz) 4.286 bit[3] 0/1 NTSC44 (60 Hz) 4.433618 bit[4] 0/1 PAL M (60 Hz) 3.575611 bit[5] 0/1 PAL N (50 Hz) 3.582056 bit[6] 0/1 PAL 60 (60 Hz) 4.433618 bit[10:7] reserved set to 0 bit[11] 1 reset status information `switch' in asr_status (cleared automatically) 0: disable recognition; 1: enable recognition Note: For correct operation don't change FP reg. 20h and 21h, while ASR is enabled!
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Micronas
ADVANCE INFORMATION
VCT 38xxA
FP Subaddress
Function
Default
Name
h'14e
Status of automatic standard recognition bit[0] 1 error of the vertical standard (neither 50 nor 60 Hz) bit[1] 1 detected standard is disabled bit[2] 1 search active bit[3] 1 search terminated, but failed bit[4] 1 no color found bit[5] 1 standard has been switched (since last reset of this flag with bit[11] of asr_enable) bit[4:0]
00000 all ok 00001 search not started, because vwin error detected
0
ASR_STATUS VWINERR DISABLED BUSY FAILED NOCOLOR SWITCH
(no input or SECAM L)
00010 search not started, because detected vert. standard 0x1x0 01x00 01x10 10000
not enabled search started and still active search failed (found standard not correct) search failed, (detected color standard not enabled) no color found (monochrome input or switch betw. CVBS/SVHS necessary) writing to this register will also initialize the standard luma selector VIN1 VIN2 VIN3 VIN4 chroma selector CIN1 CIN2 IF compensation off 6 dB/Okt 12 dB/Okt 10 dB/MHz only for SECAM chroma bandwidth selector narrow normal broad wide adaptive/fixed SECAM notch filter enable luma lowpass filter hpll speed no change terrestrial vcr mixed status bit, write 0, this bit is set to 1 to indicate operation complete. INSEL 00 VIS
h'21
Input select: bit[1:0] 00 01 10 11 bit[2] 0 1 bit[4:3] 00 01 10 11 bit[6:5] 00 01 10 11 0/1 0/1 00 01 10 11 bit[11]
0
CIS
00
IFC
01
CBW
bit[7] bit[8] bit[10:9]
FNTCH LOWP HPLLMD
h'22
Available for versions with panorama scaler only! picture start position, this register sets the start point of active video, this can be used e.g. for panning. The setting is updated when 'sdt' register is updated.
0
SFIF
h'23
luma/chroma delay adjust. The setting is updated when 'sdt' register is updated. bit[5:0] reserved, set to zero bit[11:6] luma delay in clocks, allowed range is +1 ... -7
0
LDLY
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VCT 38xxA
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FP Subaddress
Function
Default
Name
h'2f
YCrCb mode control register bit[6:0] reserved (set to 0) bit[7] 1 ADC over-/underflow (has to be reset after read if used) bit[8] 0 disable/enable YCrCb bit[9] ADC range 0 nominal input amplitude (350 mV) 1 extented input amplitude (500 mV) bit[11:10] reserved (set to 0) Note: Activate the YCrCb mode by - enabling YCrCb - selecting simple PAL or NTSC M, svhs=1, comb=0 in the std register - setting cbw=2 in the insel register Comb Filter
0
YCrCb
h'27
comb filter control register bit[0] 0 comb coefficients are calculated for luma/chroma 1 comb coefficients for luma are used for luma and chroma bit[1] 0 luma comb strength depends on signal amplitude 1 luma comb strength is independent of amplitude bit[2] 0 reduced comb booster 1 max comb booster bit[4:3] 0..3 comb strength for chroma signal bit[6:5] 0..3 comb strength for luma signal bit[11:7] 0..31 overall limitation of the calculated comb coefficients 0 no limitation 31 max limitation (1/2) Color Processing
0
CMB_UC CC
0 1 3 2 0
DAA KB KC KY CLIM
h'30
Saturation control bit[11:0] 0...4094 (2070 corresponds to 100% saturation) 4095 disabled (test mode only) amplitude killer level (0:killer disabled) amplitude killer hysteresis NTSC tint angle, 512 = /4 DVCO
2070
ACC_SAT
h'39 h'3a h'dc
25 5 0
KILVL KILHY TINT
h'f8 h'f9
crystal oscillator center frequency adjust, -2048 ... 2047 crystal oscillator center frequency adjustment value for line-lock mode True adjust value is DVCO - ADJUST. For factory crystal alignment, using standard video signal: set DVCO = 0, set lock mode, read crystal offset from ADJUST register and use negative value for initial center frequency adjustment via DVCO. crystal oscillator line-locked mode, lock command/status write: 100 enable lock 0 disable lock read: 0 unlocked >2047 locked crystal oscillator line-locked mode, autolock feature. If autolock is enabled, crystal oscillator locking is started automatically. bit[11:0] threshold; 0: autolock off
-720
read only
DVCO ADJUST
h'f7
0
XLCK
h'b5
400
AUTOLOCK
42
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VCT 38xxA
FP Subaddress
Function
Default
Name
FP Status h'12 general purpose control bits bit[2:0] reserved, do not change bit[3] vertical standard force bit[8:4] reserved, do not change bit[9] disable flywheel interlace bit[11:10] reserved, do not change to enable vertical free run mode set vfrc to 1 and dflw to 0 standard recognition status bit[0] 1 vertical lock bit[1] 1 horizontally locked bit[2] no signal detected bit[3] 1 color amplitude killer active bit[4] 1 disable amplitude killer bit[5] 1 color ident killer active bit[6] 1 disable ident killer bit[7] 1 interlace detected bit[8] 1 no vertical sync detection bit[9] 1 spurious vertical sync detection bit[11:10] reserved input noise level number of lines per field, P/S: 312, N: 262 vertical field counter, incremented per field measured sync amplitude value, nominal: 768 (PAL), 732 (NTSC) measured burst amplitude firmware version number bit[7:0] internal revision number bit[11:8] firmware release status of macrovision detection bit[0] AGC pulse detected bit[1] pseudo sync detected bit[11:0] bit[11:0] first line of macrovision detection window last line of macrovision detection window Horizontal Scaler
1)
GPC 0 1 VFRC DFLW
h'13
-
ASR
h'14 h'cb h'15 h'74 h'36 h'f0
read only read only
NOISE NLPF VCNT
read only read only read only
SAMPL BAMPL SW_VERSION
h'170
read only
MCV_STATUS
h'171 h'172
6 15
MCV_START MCV_STOP
these registers are updated when the scaler mode register is written 0 SCMODE MODE
h'40
scaler mode register bit[1:0] scaler mode 0 linear scaling mode 1 nonlinear scaling mode, 'panorama' 2 nonlinear scaling mode, 'waterglass' 3 reserved bit[10:2] reserved, set to 0 bit[11] scaler update 0 start scaler update command, when the registers are updated the bit is set to 1
SCUP
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VCT 38xxA
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FP Subaddress
Function
Default
Name
h'41
luma offset register 1) bit[6:0] luma offset 0..127 ITU-R output format: CVBS output format: active video length for 1-h FIFO 1) bit[11:0] length in pixels
57 57 4 1080
YOFFS
h'42 h'43
FFLIM SCINC1
scaler1 compression coefficient 1) For compression by a factor c the value c*1024 is required. bit[11:0] allowed values from 1024..4095 scaler2 expansion coefficient 1) For expansion by a factor c the value 1/c*1024 is required. bit[11:0] allowed values from 256..1024 scaler1/2 nonlinear scaling coefficient 1) scaler1 window controls 1) 5 12-bit registers for control of the nonlinear scaling scaler2 window controls 1) 5 12-bit registers for control of the nonlinear scaling
1024 SCINC2 1024 0 0 0 SCINC SCW1_0 - 4 SCW2_0 - 4
h'44
h'45 h'47 - h'4b h'4c - h'50
2.15.1.1. Scaler Adjustment In case of linear scaling, most of the scaler registers need not be set. Only the scaler mode, active video length, and the fixed scaler increments (scinc1/scinc2) must be written. The adjustment of the scaler for nonlinear scaling modes should use the parameters given in Table 2-6.
Table 2-6: Set-up values for nonlinear scaler modes Register Scaler Modes `waterglass' border 35% `panorama' border 30%
center compression 3/4 scinc1 scinc2 scinc fflim scw1 - 0 scw1 - 1 scw1 - 2 scw1 - 3 scw1 - 4 scw2 - 0 scw2 - 1 scw2 - 2 scw2 - 3 scw2 - 4 1643 1024 90 945 110 156 317 363 473 110 156 384 430 540 5/6 1427 1024 56 985 115 166 327 378 493 115 166 374 425 540 4/3 1024 376 85 921 83 147 314 378 461 122 186 354 418 540 6/5 1024 611 56 983 94 153 339 398 492 118 177 363 422 540
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VCT 38xxA
Table 2-7: Control Registers of the Fast Processor for control of the video backend functions
- default values are initializied at reset
FP Subaddress
Function
Default
Name
FP Display Control Register h'130 h'131 h'132 h'139 h'13c White Drive Red White Drive Green White Drive Blue (0...1023) (0...1023) (0...1023) 700 700 700 256 256 WDR 1) WDG 1) WDB 1) IBR IBRM
Internal Brightness, Picture (0...511), the center value is 256, the range allows for both increase and reduction of brightness. Internal Brightness, Measurement (0...511), the center value is 256, the brightness for measurement can be set to measure at higher cutoff current. The measurement brightness is independent of the drive values. Analog Brightness for external RGB (0...511), the center value is 256, the range allows for both increase and reduction of brightness. Analog Contrast for external RGB (0...511)
h'13a h'13b
256 350
ABR ACT
1) The white drive values will become active only after writing the blue value WDB, latching of new values is indicated by setting the MSB of WDB.
FP Display Control Register, BCL h'144 h'142 h'143 h'145 h'105 BCL threshold current, 0...2047 (max ADC output ~1152) BCL time constant 0...15 13 ... 1700 msec BCL loop gain. 0..15 BCL minimum contrast 0...1023 Test register for BCL/EHT comp. function, register value: 0 normal operation 1 stop ADC offset compensation x>1 use x in place of input from Measurement ADC FP Display Control Register, Deflection h'103 h'102 interlace offset, -2048..2047 This value is added to the SAWTOOTH output during one field. discharge sample count for deflection retrace, SAWTOOTH DAC output impedance is reduced for DSCC lines after vertical retrace. vertical discharge value, SAWTOOTH output value during discharge operation, typically same as A0 init value for sawtooth. EHT compensation vertical gain coefficient, 0...511 EHT compensation time constant, 0...15 --> 3.2..410 msec EHT compensation east/west gain coefficient, -1024...1023 0 7 INTLC DSCC 1000 15 0 307 0 BCLTHR BCLTM BCLG BCLMIN BCLTST
h'11f
-1365
DSCV
h'10b h'10a h'10f
0 15 15
EHTV EHTTM EHTEW
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VCT 38xxA
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FP Display Control Register, Vertical Sawtooth h'110 h'11b h'11c h'11d h'11e DC offset of SAWTOOTH output This offset is independent of EHT compensation. accu0 init value accu1 init value accu2 init value accu3 init value FP Display Control Register, East-West Parabola h'12b h'12c h'12d h'12e h'12f accu0 init value accu1 init value accu2 init value accu3 init value accu4 init value 0 OFS A0 A1 A2 A3
-1365
900 0 0
-1121
219 479
A0 A1 A2 A3 A4
-1416
1052
2.15.1.2. Calculation of Vertical and East-West Deflection Coefficients In Table 2-8 the formula for the calculation of the deflection initialization parameters from the polynominal coefficients a,b,c,d,e is given for the vertical and East-West deflection. Let the polynomial be:
P = a + b(x - 0.5) + c(x - 0.5)2 + d(x - 0.5)3 + e(x - 0.5)4 a0 a1 a2 a3
Vertical Deflection 60 Hz
a 128 b -1365.3 1083.5 c +682.7 -1090.2 429.9 d -682.7 +1645.5 -1305.8 1023.5
The initialization values for the accumulators a0..a3 for vertical deflection and a0..a4 for East-West deflection are 12-bit values. The coefficients that should be used to calculate the initialization values for different field frequencies are given below, the values must be scaled by 128, i.e. the value for a0 of the 50 Hz vertical deflection is:
a0 = (a * 128 - b * 1365.3 + c * 682.7 - d * 682.7) / 128
East-West Deflection 50 Hz
a a0 a1 a2 a3 128 b -341.3 111.9 c 1365.3 -899.6 586.8 d -85.3 84.8 -111.1 72.1 e 341.3 -454.5 898.3 -1171.7 756.5
Table 2-8: Calculation of Initialization values for Vertical Sawtooth and East-West Parabola Vertical Deflection 50 Hz
a a0 a1 a2 a3 128 b -1365.3 899.6 c +682.7 -904.3 296.4 d -682.7 +1363.4 -898.4 585.9
a4
East-West Deflection 60 Hz
a a0 a1 a2 a3 a4 128 b -341.3 134.6 c 1365.3 -1083.5 849.3 d -85.3 102.2 -161.2 125.6 e 341.3 -548.4 1305.5 -2046.6 1584.8
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VCT 38xxA
3. Text and OSD Processing 3.1. Introduction The VCT 38xxA includes a World System Teletext (WST) decoder, whose display capabilities are also used for OSD generation. In the following sections the text and OSD processing part of the VCT 38xxA will be named TPU for short. With integrated CPU, RAM and ROM, an adaptive data slicer, a display controller, and a number of interfaces, the TPU offers acquisition and display of various teletext and data services such as WST, PDC, VPS, and WSS. Fig. 3-1 shows the functional block diagram of the TPU. The TPU operates independently from the TV controller and can be controlled by software via I2C bus interface (see Section 3.14. on page 82). The TV controller is not burdened with the task of teletext decoding and communicates with the TPU via a high-level command language. The TPU performs the following tasks: - teletext data acquisition - teletext data decoding - page generation - page memory management - page display - user interface (hardware) (software) (software) (software) (hardware) (software) Memory Segment Zero Page 3.2. SRAM Interface The SRAM interface connects a standard SRAM to the internal bus structure. The address bus is 19 bit wide, addressing SRAMs up to 4 Mbit. Smaller SRAMs can also be connected. The SRAM interface has to handle 3 asynchronous data streams. The CPU needs access to every memory location of the SRAM. During VBI the slicer writes up to 22 teletext lines of 43 Bytes into the acquisition scratch memory. During text display the display controller copies teletext rows from display memory into its internal row buffer. On VCT 38xxA the SRAM interface of the TPU is connected to the memory bus of the TV controller. This is done to save pins and to give the TV controller faster access to the display memory. Refer to DMA Interface (chapter 5.9. on page 96) for more details. After reset the TPU will not use the SRAM interface until receiving the I2C command "DRAM_MODE" (see Section 3.12. on page 68). Stack Page OSD Buffer I/O Page Extra Page Character ROM Program ROM Absolute Address 0000 - 00FF 0100 - 01FF 0100 - 019F 0200 - 02FF 0300 - 037F 5000 - 7FFF D000 - FFFF IRQ Reset NMI Control Word 3.3. Text Controller The TPU operates with its own 65C02 core running at 10.125 MHz. The core can address up to 64 kBytes of memory. The CPU memory contains 640 Bytes RAM, 12 kBytes program ROM and 12 kBytes character ROM. The character ROM holds the font data and is separated from the program ROM to save CPU time. The CPU can still access the character ROM via a DMA interface including wait cycles. The display controller can also access the CPU memory via the same DMA interface. By this means it is possible to locate part of the character font in program ROM or part of the program code in character ROM. Table 3-1: Memory map of text controller Interrupt Vector Absolute Address (High Byte, Low Byte) FFFF, FFFE FFFD, FFFC FFFB, FFFA FFF9
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VCT 38xxA
ADVANCE INFORMATION
TPU
Clamping AGC
ADC
Slicer
I2C Bus Interface
Program RAM
Program ROM
65C02
SRAM Interface
Timer Interrupt Watchdog
DMA Interface
WST Layer
Sync Interface
Character ROM
OSD Layer
Color & Prio Interface
Fig. 3-1: Block diagram of the TPU
48
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VCT 38xxA
3.5. Teletext Page Management
Zero Page Stack Page I/O Page Extra Page
0000
1000
12K Character ROM
As a state-of-the-art teletext decoder, the TPU is able to store and manage a sufficient number of teletext pages to absorb the annoying transmission cycle times. The number of available pages is only limited by the memory size. With an intelligent software and a 4-Mbit SRAM it is possible to store and to control more than 500 teletext pages. The management of such a data base is a typical software task and is therefore performed by the 65C02. Using a fixed length page table with one entry for every possible page, the software distributes the content of the acquisition scratch buffer among the page memory. The page size is fixed to 1 kByte, only ghost rows are chained in 128-Byte segments to avoid unused memory space. A stored teletext page cannot be displayed directly, because of the row-adaptive transmission and the level 2 enhancements (row 26-29). Therefore, the CPU has to transfer the selected teletext page into a display page buffer, adding extra data such as character set extension and non-spacing attributes.
DATA ADR
8000
12K Program ROM
D000
DMA Interface
ADR
DATA BE
3.5.1. Memory Manager
Display
BUSREQ
65C02
RDY
The Memory manager is the core of the internal TPU firmware. Most of the acquisition and display related functions are controlled by this management.
Fig. 3-2: Memory environment of text controller
3.4. Teletext Acquisition
Acquisition
The only task of the slicer circuit is to extract teletext lines from the incoming composite video signal and to store them into the acquisition scratch buffer of the internal/external SRAM. No page selection is done at this hardware level. Four analog sources can be connected, thus it is possible to receive text from one channel while watching another on the screen. After clamping and AGC amplifier the analog video signal is converted into binary data. Sync separation is done by a sync slicer and a horizontal PLL, which generate the horizontal and vertical timing. By these means, no external sync signals are needed and any available signal source can be used for teletext reception. The teletext information itself is acquired using adaptive slicers on bit and byte level with soft error detection to decrease the bit error rate under bad reception conditions. The slicer can be programmed to different bit rates for reception of PAL, NTSC or MAC world system teletext as well as VPS, WSS, or CAPTION signals.
Scratch Memory
Page Table
Memory Manager
Page Memory
Display Memory
Display Controller
Fig. 3-3: Memory Manager
Micronas
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VCT 38xxA
3.5.2. Memory Organization The upper end of the memory is defined by the SRAM size, the lower end can be defined with the PAGE_MEMORY command. Default memory organization is shown in Fig. 3-4. SRAM 08 00 00 = 4Mbit
ADVANCE INFORMATION
The memory organization depends on available SRAM size. If external SRAM is not available, there is only one display bank for OSD and teletext and the page memory starts at a different location (see Table 3-1).
3.5.3. Page Table The memory management is based on a fixed size page table, which has entries for every hexadecimal page number from 100 to 8FF. The page table starts with page 800 and contains a 2-Byte page pointer for every page. The page table can be read with the command READ_PAGE_INFO sending the page number and reading the 2-Byte page pointer containing: - SRAM pointer
02 00 00 = 1Mbit
Page Memory n x 1 kByte
00 80 00 = 256Kbit
- cycle flag - memory flag - subpage flag
00 40 00 Display Bank 4 kBytes TTX Display Bank 4 kBytes Acquisition Scratch 4 kBytes Page Table 4 kBytes Fig. 3-4: Memory organization Table 3-1: Memory Organisation
Memory Segment Address Display Bank TTX Bank Page Table Acquisition Scratch Page Memory SRAM Size 128k h'3000 h'2000 h'0000 h'1000 h'4000 19k h'4000 h'4000 h'0000 h'1000 h'1800 16k h'3000 h'3000 h'0000 h'1000 h'1800 3k h'0000 h'0000 no no no
- update flag - protection flag
00 30 00
The SRAM pointer gives the location where the page is stored in memory. The page size is fixed to 1 kByte, only ghost rows are allocated dynamically. The cycle flag will be set as soon as this page is detected in the transmission cycle even if it cannot be stored in memory. Only if the page is really stored in memory, the memory flag will be set. The subpage flag will be set for every page in cycle if the page subcode is different from 0000H or 3F7FH. The update flag is set every time a page is stored and will be reset only for the display page after updating the display memory. A page with protection flag set will never be removed from memory. The memory manager uses page priorities to decide which pages should be stored or removed from memory. If no more memory is available, pages with lowest priority are removed automatically and the higher priority pages are stored at their place. By setting the page priority the programmer has control over the memory management. The page table is fully controlled by the memory manager and should never be written by external software. To change the page table flags the command CHANGE_PAGE_INFO can be used.
00 20 00
00 10 00
00 00 00
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VCT 38xxA
Table 3-2: Page Table Format Index 000 001 ... 100 ... 1F0 ... 7FE 7FF
end magazine 7 hexadecimal pages (e.g. TOP) Cycle Flag Memory Flag Subpage Flag 11-bit SRAM Pointer Update Flag Protect Flag
2-Byte Page Pointer
start magazine 8
priority
status
subcode req
subcode in
control language
4-11 12-14
row flag row flag row flag row flag
0-7 8-15 16-23 24-31
ghost row pointer subpage pointer
8 Byte
packet x/00 packet x/01
8 Byte
1 kByte page data
packet x/24 24 Byte
mag
page
index
subcode subcode high low
Fig. 3-5: Page format
Micronas
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VCT 38xxA
3.5.4. Ghost Row Organization Page-related ghost rows are stored in blocks of 128 Bytes. These ghost blocks are linked together using 2-Byte ghost row pointers. The first pointer can be found in the basic page, all following pointers are part of the block header. A zero pointer indicates the end of the chain.
ADVANCE INFORMATION
Table 3-3: Ghost Row Identification Row Number Tag 000 001 Row empty row 25 row 26 row 27 row 28 row 29 row 30 row 31
Page Table
page pointer
ghost pointer
010 011
page 100
100 101 110
ghost pointer
111
ghost block
4-bit designation code
3-bit row number
0000
ghost block
`aa' `aa' `aa' row 1 row 2 row 3 ghost row pointer
Fig. 3-6: Ghost row organization
Every ghost block contains 3 ghost rows which can be identified by 3 row identification bytes in the block header. The row identification contains designation code and row number. The row number is reduced to a 3-bit tag. All ghost rows in one block belong to the same page. If the memory manager removes a page from memory, the linked ghost blocks will also be removed.
8 Byte block header 40 Byte row 1 data 40 Byte row 2 data 40 Byte row 3 data
Fig. 3-7: Ghost block structure
3.5.5. Subpage Manager Any page in cycle can have a number of subpages, identified by subcode. In normal mode the subpage manager will acquire only one subpage of every requested page. This subpage can be any if subcode FFFF is requested or it will be selected according to the requested subcode. After a PAGE_REQUEST command with subcode F0xx, the subpage manager will acquire all subpages of the requested page. The subpages will be chained in the same order as they are transmitted, i.e. every new subcode will be added at the end of chain. The page table entry points to the subpage which was transmitted first after the page request. The
READ_PAGE_INFO command will reply the page table pointer and the actual number of subpages in chain. After a PAGE_REQUEST command with subcode F1xx, the subpage manager will acquire all subpages of the requested page but will allocate only a limited amount of memory to store these subpages. The parameter "page subcode low" will define the length (in number of subpages) of a ring buffer in page memory which will hold the recently received subpages. In this case, the READ_PAGE_INFO command will return an index pointing to the most recently updated subpage in chain, together with the subcode of this page.
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VCT 38xxA
3.6. WST Display Controller The display controller reads data from a display page buffer in the internal/external SRAM. The display page buffer is organized in rows which are separated into level 1 data such as character codes and spacing attributes and into level 2 data, such as character set extension and non-spacing attributes. To limit the memory amount for level 2 data, a slightly modified stack model is used, in which one pointer bit for every character location indicates the presence of additional parallel attributes. Fig. 3-9 shows the organization of the stack row buffer. In this stack model the number of non-spacing attributes per row is limited to 40, which agrees with the WST and CEPT specification.
The DISPLAY_PAGE_REQUEST command searches and displays a page according to the requested display subcode. The search starts from page table and continues through the subpage chain if there is any. A rolling header will be displayed if the requested subpage cannot be found in memory. A requested display subcode FFFF (don't care subcode) will only search and display the first subpage in chain, thus there is no rolling subpage anymore. A DISPLAY_PAGE_REQUEST command with subcode F0xx (follow subcode) will search and display the last received subpage in chain, thus it is possible to request all subpages in background while still showing rolling subpages in display.
subpage pointer
Page Table
page pointer
Level 2 Buffer
1 Char 3 Attr. 1 Char 3 Attr. 1 Char 3 Attr. 0 Char 3 Attr.
Pointer
0 0 1 0 0 1 0 0 0 1
Level 1 Buffer
Char 1 Char 2 Char 3 Char 4 Char 5 Char 6 Char 7 Char 8 Char 9 Char 10
page 100 subcode 0003
subpage pointer
1 Char 6Attr. 1 Char 6 Attr. 0 Char 6 Attr. 1 Char 10 Attr. 1 Char 10 Attr. 1 Char 10 Attr.
page 100 subcode 0001
0000
page 100 subcode 0002
0 Char 36 Attr. 0 0 0
1 0 0 0 0
Char 36 Char 37 Char 38 Char 39 Char 40
Fig. 3-8: Subpage organization
0
Fig. 3-9: Stack Row Buffer
The display controller includes two row buffers. The first row buffer holds a copy of a teletext row from the display page buffer. This decreases the data rate through the SRAM interface by a factor of 10 or 8, because new teletext row data is needed only after 10 lines in PAL or 8 lines in NTSC mode. The second row buffer stores all display attributes in parallel, to allow level 2 display without additional decoding.
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VCT 38xxA
To present a WST level 2 display, the teletext display controller has to evaluate the following attributes in parallel, that is for every character location: - 10-bit character code - 5-bit foreground color - 5-bit background color - 2-bit size - 5-bit flash - 1-bit invert - 1-bit separated - 1-bit conceal - 1-bit underline - 1-bit boxing/window Additional attributes are defined to improve the display of CAPTION and OSD text: - 1-bit italics - 1-bit shadow - 1-bit color mode The display controller delivers 5-bit digital color information, a shadow signal for contrast reduction, and a fast blank signal. The color bus is used to address the color-lookup-table (CLUT) in the video processor. By this means, the full level 2 color spectrum can be displayed.
ADVANCE INFORMATION
54
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VCT 38xxA
DISPLAY_TTX_POINTER. Other banks can be used to store any kind of display data in level 1 or level 2 format. Switching between these banks is fast and can be programmed with the command DISPLAY_POINTER. Bank switching allows generation of OSD menus without affecting the teletext display.
3.7. Display Memory The TPU supports a variable number of display memories, each 4 kBytes large. One bank is used to store the display information of the selected teletext page. The bank location can be defined with the command
autoincrement
Row 0
40 Byte level 1
40-bit pointer
40 Byte level 2
full row attr.
Row 1
40 Byte level 1
40-bit pointer
40 Byte level 2
full row attr.
Display Bank
Row 46
40 Byte level 1
40-bit pointer
40 Byte level 2
full row attr.
Row 0
40 Byte level 1
40-bit pointer
40 Byte level 2
full row attr.
Row 1
40 Byte level 1
40-bit pointer
40 Byte level 2
full row attr.
TTX Display Bank
Row 25
40 Byte level 1
40-bit pointer
40 Byte level 2
full row attr.
SRAM
Fig. 3-10: Display memory organization (level 2)
Micronas
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VCT 38xxA
Table 3-5: Full row attribute
+ 55H Bit 7 6 5 4 to 0 R/W Reset Full Row Attribute Function 1 = row is displayed blank 0 = row is displayed using row data 1 = row is displayed in double height 0 = row is displayed in normal height 1 = row is displayed in level 2 mode 0 = row is displayed in level 1 mode 5-bit value defining full row background color
ADVANCE INFORMATION
Table 3-7: Level 2 parallel attributes
7
P P P P P P P P P P P
6
0 0 1 1 1 1 1 1 1 1 1 1
5
0 1 0 1 1 1 1 1 1 1 1 1
4
3
2
Color Color Flash
1
0
Function
Foreground Color Background Color Flash Mode
0 0 0 0 1 1 1 1 1
0 1 1 1 0 0 0 0 1
L 0 1 1 0 0 1 1 0 DH 0 1 0 1 0 1 0
Set DW U I C W S IT CM
Character Set Size Underline/Separated Inverted Conceal Window/Boxing Shadow Italic Color Mode
Table 3-6: Level 1 spacing attributes
Code 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Function Alpha Black Alpha Red Alpha Green Alpha Yellow Alpha Blue Alpha Magenta Alpha Cyan Alpha White Flash Normal Flash Off Boxing Off Boxing On Size Normal Size Double Height Size Double Width Size Double Mosaic Black Mosaic Red Mosaic Green Mosaic Yellow Mosaic Blue Mosaic Magenta Mosaic Cyan Mosaic White Conceal Contiguous Mosaic Separated Mosaic ESC Black Background New Background Hold Mosaic Release Mosaic set at set at set at set at set at set at set mosaic mode and foreground color of following mosaic characters select character set 1 set at set at double set at double set at Action Notes set alpha mode and foreground color of following alpha characters select character set 0
P
Table 3-8: Color look-up table
4
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
3
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 x
2
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 x
1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 x
0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 x
Display Color
Black Red Green Yellow Blue Magenta Cyan White Transparent Reduced Red Reduced Green Reduced Yellow Reduced Blue Reduced Magenta Reduced Cyan Reduced White Programmable
Table 3-4: Flash modes
4
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
3
0 0 0 1 1 0 0 1 1 0 0 1 1 0 0
2
0 0 1 0 1 0 1 0 1 0 1 0 1 0 1
1
0 0 0 0 0 1 1 1 1 1 1 1 1 x x
0
0 1 1 1 1 0 0 0 0 1 1 1 1 x x
Function
Off Normal Normal Fast Phase 1 Normal Fast Phase 2 Normal Fast Phase 3 Inverted Inverted Fast Phase 1 Inverted Fast Phase 2 Inverted Fast Phase 3 Color Table Color Table Phase 1 Color Table Phase 2 Color Table Phase 3 Incremental Decremental
Shaded attributes are default at start of each display row.
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VCT 38xxA
The pixel clock can be either 10.125 MHz or 20.25 MHz. To get 10-bit pixel information from the character font, two memory cycles are needed. The character font is part of the mask-programmable ROM, but supplied with its own bus structure (see Fig. 3-2 on page 49). By this means the data transfer between character ROM and teletext display controller does not stop the CPU. Both bus structures are connected via a memory interface which allows cross-connections using DMA or wait cycles. If the character font size exceeds 12 kBytes, part of the character font can be shifted into the program ROM which causes DMA cycles. Therefore only less frequently used characters should be placed into the program ROM. Vice versa seldom used CPU code can be put into the character ROM. The WST specification defines a number of 7-bit code tables, which are filled with 96 characters only (the MSB is used for parity check). In the G0 code table some characters have several language dependent variations. Additionally characters from the G0 code table can be combined with diacritical marks from the G2 code table (row 26). Furthermore different code tables are defined for languages like cyrillic, greek or arabic. Thus it is not possible to simply transform the code tables into a continuous character font ROM without getting unused ROM space and multiple defined character fonts. This problem is solved by implementing a character code mapping (see Fig. 3-11 on page 58). The 5 MSBs of each character code are mapped into another 5-bit code which is then used to address the character font ROM. By this means the whole character font is subdivided into 32 blocks of 32 characters which can freely be distributed over the 4 character sets. The character code mapping is implemented as RAM and can be programmed by software. After reset the TPU initializes the mapping RAM for standard WST latin code tables. The TV controller can select predefined mappings for latin, cyrillic and arabic teletext via the command DISPLAY_MODE (see Table 3-16 on page 70). The same command allows selection of a user defined mapping which has to programmed in advance using command USER_MAPPING.
3.8. Character Generator Characters are addressed using a 10-bit character code. The 2 MSBs of the character code define 1 of 4 character sets. Character set selection is done using level 2 parallel attributes (see Table 3-7 on page 56). Each character set contains 224 characters. The first 32 characters in each character set are reserved for control codes (see Table 3-6 on page 56). On a single screen, 896 different characters can be displayed. Characters can be displayed in several pixel resolutions provided that the according font is available. The character generator supports horizontal resolution of 8 or 10 pixel/char and vertical resolution of 8, 10, or 13 lines/char. Characters can be combined without separating borders to create more complex character definitions (e.g. kanji or icons). Table 3-9: Character resolutions
matrix (h x v) char/sc reen (PAL) char/sc reen (NTSC) osd width # char in 12k font # char in 20k font
single character 8x8 10 x 8 8 x 10 10 x 10 8 x 13 10 x 13 40 x 32 40 x 32 40 x 26 40 x 26 40 x 20 40 x 20 40 x 28 40 x 28 40 x 22 40 x 22 40 x 17 40 x 17 32s 40s 32s 40s 32s 40s 1600 1280 1280 1024 800 640 2560 2048 2048 1638 1280 1024
combined character (2 x 2) 16 x 16 20 x 16 16 x 20 20 x 20 16 x 26 20 x 26 20 x 16 20 x 16 20 x 13 20 x 13 20 x 10 20 x 10 20 x 14 20 x 14 20 x 11 20 x 11 20 x 8.5 20 x 8.5 32s 40s 32s 40s 32s 40s 400 320 320 256 200 160 640 512 512 409 320 256
combined character (2 x 1) 16 x 10 16 x 13 20 x 13 20 x 26 20 x 20 20 x 20 20 x 22 20 x 17 20 x 17 32s 32s 40s 640 400 320 1024 640 512
combined character (1x 2) 10 x 16 40 x 16 40 x 14 40s 640 1024
Micronas
57
VCT 38xxA
3.8.1. Character Code Mapping
ADVANCE INFORMATION
10-bit Character Code = 2-bit Character Set (level 2) + 8-bit Character Value (level 1) Character Set 0 000H G0 G0 G0 National National National National Character Set 1 100H G1 G0 G1 National National National National Character Set 2 200H G2 G2 G2 User User User User Character Set 3 300H G3 G3 G3 User User User User
24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 08 09 10 11 12 13 14 15 00 01 02 03 04 05 06 07
Character ROM 12800 Byte Font Pointer
00 01 02 03 04 05 06 07 08 09 10 11
080H
180H
Mapping RAM 32 x 5 bit
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
280H
380H
G0 G0 G0 National National National National G1 G1 G2 G2 G2 User User User User G3 G3 G3 Greek Greek Cyrillic Cyrillic Cyrillic Hebrew Arabic Arabic Arabic Farsi
block of 32 char
31
Fig. 3-11: Character code mapping
58
Micronas
ADVANCE INFORMATION
VCT 38xxA
3.8.2. Character Font ROM The character font ROM is mask-programmable. Design of customer specific characters (user font) is supported by a WindowsTM based PC tool named MOFA (Micronas OSD and Font Assembler). In combination with the VCT 38xxA emulator board it is possible to download character fonts and verify them on the TV screen.
Fig. 3-12: Character font ROM
Micronas
59
VCT 38xxA
3.8.3. Latin Font Mapping
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Fig. 3-13: Latin font mapping
60
Micronas
ADVANCE INFORMATION
VCT 38xxA
3.8.4. Cyrillic Font Mapping
Fig. 3-14: Cyrillic font mapping
Micronas
61
VCT 38xxA
3.8.5. Arabic Font Mapping
ADVANCE INFORMATION
Fig. 3-15: Arabic font mapping
62
Micronas
ADVANCE INFORMATION
VCT 38xxA
3.8.6. Character Font Structure
MSB 9 Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 Line 7 Line 8 Line 9 Line 10
LSB 0 Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 Line 7 Line 8 Line 9 Line 10 Line 11 Line 12 Line 13
MSB 7
LSB 0
Character Font
Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 Line 7 Line 8 Line 9 Line 10 Line 1 Line 2 Line 3 Line 4 `@` `@` `@` `@` `@` `@` `@` `@` `@` `@` `A` `A` `A` `A`
Character Font
Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 Line 7 Line 8 Line 9 Line 10 Line 11 Line 12 Line 13 Line 14 Line 15 Line 16 Line 1 Line 2 Line 3 `P` `P` `P` `P` `P` `P` `P` `P` `P` `P` `P` `P` `P`
Extension Font
Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 Line 7 Line 8 Line 9 Line 10 Line 1 Line 2 Line 3 Line 4 `@` `@` `@` `@` `@` `@` `@` `@` `@` `@` `D` `D` `D` `D` `A` `A` `A` `A` `A` `A` `A` `A` `A` `A` `E` `E` `E` `E` `B` `B` `B` `B` `B` `B` `B` `B` `B` `B` `F` `F` `F` `F` `C` `C` `C` `C` `C` `C` `C` `C` `C` `C` `G` `G` `G` `G`
`Q` `Q` `Q`
Fig. 3-17: Font structure 8 x 13
Fig. 3-16: Font Structure 10 x 10
Micronas
63
VCT 38xxA
3.9. National Character Mapping Table 3-10: Character set options Option Bits
C14,C13,C12 000 001 010 011 100 101 110 111 6 English French Swedish Czech German Spanish Italian Estonian Polish French Swedish Czech German Serbian Italian Estonian 38
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Character Set
40 English (US) French Swedish Czech German Spanish Italian Estonian 55 English French Swedish Turkish German Spanish Italian Estonian 70 English (US) Slovakian Hungarian Serbian Albanian Polish Turkish Rumanian 128 programmable programmable programmable programmable programmable programmable programmable programmable
Table 3-11: Language codes Code 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25-255 Language
English French Swedish, Finnish Czech German Spanish Italian Estonian, Finnish English (US) Slovakian Hungarian Serbian, Croatian, Slovene Albanian Polish Turkish Rumanian Cyrillic (Russian, Bulgarian) Greek Cyrillic (Serbian, Montenegro) YU Latin Arabic Hebrew Farsi Lettish, Lithuanian Cyrillic (Ukrainian) not defined
64
Micronas
ADVANCE INFORMATION
VCT 38xxA
Table 3-12: National option mapping Language
2/3 Albanian Czech English English (US) Estonian, Finnish French German Hungarian Italian Polish Rumanian Serbian, Croatian Slovakian Spanish Swedish, Finnish Turkish YU Latin 5/15 5/15 2/3 5/15 5/15 9/3 5/15 5/15 2/3 5/15 5/15 5/15 5/15 9/0 5/15 13/6 5/15 2/4 2/4 12/9 2/4 2/4 11/11 8/1 2/4 9/2 2/4 14/3 14/1 2/4 12/9 2/4 14/1 10/13 2/4 4/0 13/12 13/13 4/0 4/0 11/12 8/5 15/0 9/14 9/3 13/15 10/14 13/12 13/13 9/15 9/14 10/8 13/12 5/11 13/2 10/11 5/11 14/4 8/13 9/1 8/13 8/4 14/0 13/8 10/5 13/2 10/11 8/3 8/13 14/14 13/2 5/12 12/12 12/13 5/12 13/5 8/14 9/7 8/14 8/14 9/0 12/7 14/14 12/12 12/13 9/3 8/14 8/14 12/12
G0/G1 Table Position
5/13 12/3 12/11 5/13 15/4 12/12 8/2 8/15 10/1 5/13 15/8 14/11 12/3 12/11 8/4 9/13 8/0 12/3 5/14 11/12 8/4 5/14 14/6 8/15 8/8 14/6 12/15 5/14 13/3 10/6 11/12 8/4 9/4 8/15 8/15 11/12 5/15 9/1 15/13 5/15 13/0 11/10 5/15 13/0 11/15 5/15 9/4 15/1 13/0 15/13 9/2 13/0 10/12 13/0 6/0 13/13 9/3 6/0 14/7 11/13 9/5 14/0 9/3 8/2 10/9 10/15 13/13 9/3 9/9 9/3 15/1 13/13 7/11 13/3 8/3 7/11 14/5 8/10 8/7 8/10 9/4 8/5 13/9 8/7 13/3 8/3 8/12 8/10 14/15 13/3 7/12 12/13 12/0 7/12 15/6 8/11 9/8 8/11 8/11 9/6 13/7 14/15 12/13 12/0 9/11 8/11 8/11 12/13 7/13 13/1 9/2 7/13 15/5 12/13 8/9 8/12 8/3 9/5 15/9 12/5 13/1 9/2 9/5 9/12 9/0 13/1 7/14 11/13 11/13 7/14 15/7 8/12 9/0 9/10 8/12 8/6 13/11 8/8 11/13 11/13 8/5 8/12 8/12 11/13
Micronas
65
VCT 38xxA
3.10.Four-Color Mode In "Four-Color Mode" the color depth of single or multiple characters can be increased to 4 colors (e.g. to display icons or 3-D effects). A special font organization is required because two consecutive characters will be combined. The number of 4-colored characters is only limited by font size. The "Four-Color Mode" is controlled via the level 2 parallel attribute "Color Mode". Setting the bit CM to 1 activates the "Four-Color Mode" until the end of row or until the bit CM is set to 0 again. At the start of each display row the "Four-Color Mode" is disabled. A character with active "Four-Color Mode" attribute will be combined with its font neighbor to define a 2 bit/pixel character matrix. The 2 additional colors are derived from the active foreground and background colors by inverting bit 3 of the color code. Using the programmable part of the CLUT it is possible to display characters in 4 out of 4096 colors. If the "Four-Color Mode" attribute is set for a character with even character code n, this character is combined with its font neighbor addressed by code n + 1. If the "Four-Color Mode" attribute is set for a character with
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odd character code, this character is combined with itself. The neighbor character does not change the definition of foreground and background pixel which is used to control flash and mix mode.
Table 3-13: Color Allocation Pixel Definition Character n 0 1 0 1 Character n+1 0 0 1 1 background foreground background .xor. 8 foreground .xor. 8 Color Allocation
Matrix of Character n
Matrix of Character n+1
4 Color Display
00
10
+
=
01 11
Fig. 3-18: Four-color mode
66
Micronas
ADVANCE INFORMATION
VCT 38xxA
3.11.OSD Layer Apart from the WST layer, there is an additional OSD layer on chip. The OSD layer accesses the CPU memory via DMA to read text, display attributes, and character font information. The color outputs of the OSD layer can have higher priority than the WST layer outputs. Thus, it is possible to overlay the teletext display with an additional layer for user guidance (see Fig. 3- 19).
Code 01 02 03 04 05 06 07 Function Underline On Underline Off Flash On Flash Off Italics On Italics Off Transparent Shadow END CR ASCII Character Control Code layer becomes transparent layer becomes transparent and contrast is reduced to 66% end of layer end of text line using font 1 or font 2 Only one control code per character is allowed. Depending on OSD Mode, the control code defines either color or character set. bit 0 = foreground color blue bit 1 = foreground color green bit 2 = foreground color red bit 3 = background color blue bit 4 = background color green bit 5 = background color red bit 6 = replace white by transparent bit 7 = 1 bit 0 = bit 7 of character code bit 1 = bit 8 of character code bit 2 = bit 9 of character code bit 3 = bit 4 = bit 5 = bit 6 = latching shift to character set bit 7 = 1 Notes only for 13 scanlines/character
Full Screen Layer
08 0C 0D 0E - 7F 80 - FF
WST Layer
Color
OSD Layer
Fig. 3-19: Display layer
Character Set
The OSD layer reads text strings addressed by a programmable text pointer. Codes smaller than 80h will address the character font, codes greater or equal 80h are interpreted as control codes to change color or character set (see Table 3-14). After reading a control code the OSD layer will do an additional read to get the next character code.
Shaded attributes are default at start of each text line.
Micronas
67
VCT 38xxA
3.12.Command Language The TPU supports a command language, allowing the TV controller to start complex processing inside the TPU with simple commands. The TV controller is not burdened with time consuming tasks like page searching or data shuffling. Table 3-15 lists all available commands. For a more detailed description of the command language see Table 3-16. Table 3-15: Command language cross reference
Code Dec. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Code Hex. 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 Command Name Dummy Reset Escape Version Test Test DRAM Mode Acquisition Mode Display Mode Display TTX Pointer Display Pointer Display Clear Page Request Display Time Pointer Read DRAM Size Read VPS Read Quality Read Display Mode Read Reset Source Read Rolling Header Read Page Info Read Page Row Change Page Info Search MPET Read Display Page Page Memory Display Page Request Page Table Reset Search Next Page Read Page Cycle Read TOP Code Read Rolling Time Copy Page Row Copy Data Search Next TOP Code Read Ghost Row No. Write Parameter 0 0 0 0 0 0 3 5 4 2 3 2 8 2 0 0 0 0 0 0 2 5 3 0 0 2 5 0 3 0 2 0 8 7 3 6 No. Read Parameter 0 0 0 2 0 0 0 2 0 0 0 0 3 0 3 15 4 4 1 24 7 40 0 1 + (n*4) 4 0 0 0 6 9 2 8 0 0 4 40
ADVANCE INFORMATION
The application software has to send commands to the TPU via I2C bus using the command subaddresse SUB4 (see Section 3.14.1.3. on page 83).
Status Register x000 0000 x000 0000 x000 0000 x000 0000 x000 0000 x000 0000 x000 0000 x000 0000 x000 0000 x000 0000 x000 0000 x000 0000 x0x0 0000 x000 0000 x000 0000 x0x0 0000 x000 0000 x000 0000 x000 0000 x000 0000 x000 0000 x0x0 0000 x000 0000 x0x0 0000 x000 0000 x000 0000 x000 0000 x000 0000 x0x0 0000 x000 0000 x000 0000 x000 0000 x0x0 0000 x000 0000 x0x0 0000 x0x0 0000
68
Micronas
ADVANCE INFORMATION
VCT 38xxA
Table 3-15: Command language cross reference
Code Dec. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 Code Hex. 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d Command Name Read 8/30 Row Read Priority Page Priority Search AIT Read TOP Status Search AIT Title Reset Ghost Row Status Search MPT Copy AIT Title Search Direct Choice Read Hamming Read Hamming 2 Display Column Display Fill Read BTTL Read Next Page Change BTT magazine Read WSS Read CAPTION 1 Read CAPTION 2 OSD Font Pointer Display Read Column User Character Set User ESC Character Set Full Row Attribute User Mapping No. Write Parameter 1 0 2 0 0 2 0 0 5 1 1 3 3+length 4 0 2 1 0 0 0 5 3 8 8 3 32 No. Read Parameter 40 5 0 1 + (n*4) 2 17 0 1 + (n*4) 17 1 + (n*2) 1 3 0 0 9 2 0 15 7 7 0 length 0 0 0 0 Status Register x0x0 0000 x000 0000 x000 0000 x0x0 0000 x000 0000 x0x0 0000 x000 0000 x0x0 0000 x0x0 0000 x0x0 0000 x000 0000 x000 0000 x000 0000 x000 0000 x0x0 0000 x000 0000 x000 0000 x0x0 0000 x0x0 0000 x0x0 0000 x000 0000 x000 0000 x000 0000 x000 0000 x000 0000 x000 0000
Micronas
69
VCT 38xxA
ADVANCE INFORMATION
Note: If not otherwise designated, all parameters in the following table are specified as single bytes. As write parameter magazine numbers 8 and 0 have the same meaning, as read parameter the magazine number is a true 4-bit number (e.g. magazine 8= 00001000). For write parameters the values in parentheses indicate default values after reset (in hex notation). For compatibility reasons every undefined bit in a write parameter should be set to `0'. Undefined bits in a read parameter should be treated as "don't care".
Table 3-16: Command language
Code 00 01 02 03 04 05 06 Function Dummy Reset Escape Version Test Test DRAM Mode dram mode flash inc control enable (06) (05) (FF) CPU pointer high CPU pointer low Write Parameter Read Parameter Notes no action software reset of 65C02 escape to other codes show version in OSD layer CPU pointer to text in ROM reserved for testing reserved for testing dram mode = I/O page register 028EH flash freq = flash inc / (256 * 0.00324) control enable: bit0 = C4 erase page bit1 = C5 news flash bit2 = C6 subtitle bit3 = C7 suppress header bit4 = C8 update indicator bit5 = C9 interrupted sequence bit6 = C10 inhibit display bit7 = C11 magazine parallel gain filter acquisition mode: bit0 = no slicer adaption bit1 = no bit error in framing code bit2 = limit slicer adaption init subcode: automatic subcode request after page table reset gain max: only used if bit2 = 1 filter max: only used if bit2 = 1 dram size: 000CH = 3kByte SRAM 004CH = 19kByte SRAM 0200H = 128kByte SRAM 0240H = 144kByte SRAM 0400H = 256kByte SRAM 0800H = 512kByte SRAM dram mode: see I/O page register 028EH start of page memory execute page table reset reset page table reset ghost row status reset data service status reset cycle count reset memory count reset ghost count reset priorities clear rolling header clear VPS data clear WSS data
Operational & Test Commands
07
Acquisition Mode
acquisition mode init subcode high init subcode low gain max filter max
(00) (FF) (FF) (1F) (1F)
Memory Management Commands 14 Read DRAM Size dram size high dram size low dram mode
25 27
Page Memory Page Table Reset
dram bank dram high
(00) (40)
70
Micronas
ADVANCE INFORMATION
VCT 38xxA
Table 3-16: Command language, continued
Code 42 Function Reset Ghost Row Status Write Parameter Read Parameter Notes ghost row status: bit0 = row 24 in cycle bit1 = row 25 in cycle bit2 = row 26 in cycle bit3 = row 27 in cycle bit4 = row 28 in cycle bit5 = row 29 in cycle bit6 = row 30 in cycle bit7 = row 31 in cycle ghost row status 2 Byte cycle count 2 Byte memory count 2 Byte ghost count data service status memory status = number of pages in cycle = number of pages in memory = number of ghost blocks in memory data service status: bit0 = 8/30 format 1 updated bit1 = 8/30 format 2 updated bit2 = VPS updated bit3 = WSS updated bit4 = CAPTION 1st field updated bit5 = CAPTION 2nd field updated memory status: bit0 = memory full enable: bit0 = enable priority manager border: min/max border for page priorities highest priority lowest priority border priority magazine number page number Page Related Commands 12 Page Request magazine number page number page subcode high page subcode low priority quantity start magazine number start page number number of open requests removed magazine number removed page number remove pages from memory beginning at start page if page priority is disabled, ignores start page if page priority is enabled magazine number: bit0-3 = magazine number bit4 = not used bit5 = hex request bit6 = backward request bit7 = forced request = ignore cycle flag = pointer from page table = number of subpages in chain = number of ghost rows in chain if page request with subcode F1xx = max priority in page memory = min priority in page memory = min/max border for page priorities = page with lowest priority
29
Read Page Cycle
38
Page Priority
enable border
(00) (FF)
37
Read Priority
20
Read Page Info
magazine number page number
page pointer high page pointer low subpage count ghost row count ring buffer index page subcode high page subcode low
22
Change Page Info
magazine number page number page table flags
page table flags: bit0 = protection bit1 = update bit2 = not used bit3 = not used bit4 = not used bit5 = subpage bit6 = memory bit7 = cycle
Micronas
71
VCT 38xxA
Table 3-16: Command language, continued
Code 28 Function Search Next Page Write Parameter magazine number page number search code Read Parameter magazine number page number page pointer high page pointer low subpage count ghost row count Notes
ADVANCE INFORMATION
search in page table for cycle flag magazine number: bit0-3 = magazine number bit4 = take search code bit5 = hex search bit6 = backward search bit7 = include start page search code: bit0 = search protection flag bit1 = search update flag bit2-4 = not used bit5 = search subpage flag bit6 = search memory flag bit7 = search cycle flag calculate next page number magazine number: bit0-3 = magazine number bit4 = not used bit5 = hex calculation bit6 = backward calculation bit7 = not used row 0 - 24
51
Read Next Page
magazine number page number
magazine number page number
21
Read Page Row
magazine number page number subpage number high subpage number low row number magazine number page number subpage number high subpage number low row number destination dram bank destination dram high destination dram low magazine number page number subpage number high subpage number low row number designation code
40 Byte row data
32
Copy Page Row
copy 40Byte text row from page memory into DRAM
35
Read Ghost Row
40 Byte row data
row 25 - 28
TOP Commands 40 Read TOP Status TOP status 1 TOP status 2 TOP status 1: bit0 = not used bit1 = MPT link in PLT bit2 = MPET link in PLT bit3 = AIT link in PLT bit4 = BTT in memory bit5 = MPT in memory bit6 = MPET in memory bit7 = AIT in memory TOP status 2: bit0-5 = not used bit6 = all MPET in memory bit7 = all AIT in memory code: bit0-3 = data bit6 = hamming error BTTL error: bit6 = hamming error in BTTL BTTL data: bit0-3 = data bit6 = hamming error all TOP commands then refer to this magazine number of MPTs magazine number page number subpage number high subpage number low ... search in PLT
30
Read TOP Code
magazine number page number
BTT code MPT code BTTL error 8 Byte BTTL data
50
Read BTTL
52 43
Change BTT magazine Search MPT
magazine number
(01)
72
Micronas
ADVANCE INFORMATION
VCT 38xxA
Table 3-16: Command language, continued
Code 23 Function Search MPET Write Parameter Read Parameter number of MPETs magazine number page number subpage number high subpage number low ... number of AITs magazine number page number subpage number high subpage number low ... magazine number page number 5 Byte data 12 Byte title Notes search in PLT
39
Search AIT
search in PLT
41
Search AIT Title
search in AIT magazine number: bit0-3 = magazine number (0#8) bit4-6 = not used bit7 = ignore title language data: bit0-3 = data bit6 = hamming error search in AIT and copy title into dram magazine number: bit0-3 = magazine number (0#8) bit4-6 = not used bit7 = ignore title language data: bit0-3 = data bit6 = hamming error search in BTT magazine number: bit0-3 = magazine number bit4-5 = not used bit6 = backward search bit7 = include start page code condition: low nibble = BTT code high nibble = search condition 0 = BTT code in low nibble 1 = BTT code # 0 2 = block page 3 = group page 4 = normal page 5 = subtitle page 6 = TV page 7 = block/TV page 8 = group/block/TV page 9 = subpage a = block/TV subpage b = group/block/TV subpage c = title page d = future page e = future page f = future page code: bit0-3 = BTT code bit6 = hamming error code flag: bit0 = subtitle page found bit1 = TV page found bit2 = block page found bit3 = group page found bit4 = normal page found bit5 = future page found bit6 = title page found bit7 = subpage found search in AIT
44
Copy AIT Title
magazine number page number destination dram bank destination dram high destination dram low
5 Byte data 12 Byte title
34
Search Next TOP Code
magazine number page number code condition
magazine number page number code code flag
45
Search Direct Choice
direct choice code
number of AIT entries magazine number page number ...
Micronas
73
VCT 38xxA
Table 3-16: Command language, continued
Code 36 Function Read 8/30 Row Write Parameter designation code Read Parameter 40 Byte row data Notes
ADVANCE INFORMATION
Miscellaneous Data Commands only format 1 and 2 are supported 1st byte of row data is already hamming decoded = 51H = incremented every VPS reception = biphase decoded VPS bytes 3-15 = 78H = incremented every WSS reception = 102 WSS elements from group 1 on = incremented every reception in field 1 = 3x oversampling = incremented every reception in field 2 = 3x oversampling every row 0 in cycle using time pointer updated every VBI
15
Read VPS
framing code counter 13 Byte VPS data framing code counter 13 Byte WSS data counter 6 Byte CAPTION data counter 6 Byte CAPTION data 24 Byte rolling header 8 Byte rolling time text lines hamming errors parity errors soft errors reset source
53
Read WSS
54 55 19 31 16
Read CAPTION 1 Read CAPTION 2 Read Rolling Header Read Rolling Time Read Quality
18
Read Reset Source
reset source: bit0 = clock supervision bit1 = voltage supervision bit2 = watchdog all bits in reset source are reset after read hamming Byte: bit0-3 = data bit6 = hamming error address: bit0-5 bit7 mode: bit0-4 data: bit0-6 = address = hamming error = mode = data
46
Read Hamming
hamming (8,4) Byte
data
47
Read Hamming 2
hamming (24,18) 1st Byte hamming (24,18) 2nd Byte hamming (24,18) 3rd Byte
address mode data
33
Copy Data
source dram bank source dram high source dram low length destination dram bank destination dram high destination dram low Display Commands display mode character set font mapping
copy data from DRAM to DRAM
17
Read Display Mode
display mode: bit0 = forced boxing bit1 = reveal bit2 = box bit3 = time hold bit4 = page hold bit5 = row 24 hold bit6 = row 25 hold bit7 = row 26 hold display mode: character set: font mapping: see above 6,38,40,55,70,128 0=latin 1=cyrillic/greek 2=arabic/farsi/hebrew 128=user defined
08
Display Mode
display mode character set font mapping
(18) (06) (00)
09 10
Display TTX Pointer Display Pointer
dram high dram low dram high dram low scroll counter dram high dram low
(20) (00) (20) (00) (00)
page memory is copied to TTX pointer display starts at pointer using scroll counter as line offset clear display bank beginning at pointer (26 rows * 86 Bytes)
11
Display Clear
74
Micronas
ADVANCE INFORMATION
VCT 38xxA
Table 3-16: Command language, continued
Code 13 26 Function Display Time Pointer Display Page Request Write Parameter dram high dram low (20) (20) Read Parameter Notes 8 Byte time string from packet x/00 is copied to time pointer magazine number: bit0-3 = magazine number bit4 = change display delay bit5 = display clear (on update) bit6-7 = not used subpage number: F0xx for rolling subpages display delay: delay after row 0 reception in steps of 3.24ms (255 = no update) only used if bit4 = 1 magazine number page number subpage number high subpage number low dram high dram low length Byte list ... dram high dram low length character font mode (00) font pointer high font pointer low extension font pointer high extension font pointer low dram high dram low length language 000 language 001 language 010 language 011 language 100 language 101 language 110 language 111 esc language 000 esc language 001 esc language 010 esc language 011 esc language 100 esc language 101 esc language 110 esc language 111 full row attribute number of rows start row 32 Byte mapping data (00) (01) (02) (03) (04) (05) (06) (07) (00) (00) (00) (00) (00) (00) (00) (00) Byte list ... current page in display
magazine number page number subpage number high subpage number low display delay (1E)
24
Read Display Page
48
Display Column
write to dram with increment of 86 Bytes = number of bytes in list
49
Display Fill
repeated write of 1 character to dram = number of repeated writes font mode: bit0 = 0 = reset OSD font 2 pointer bit0 = 1 = load OSD font 2 pointer with following parameters read from dram with increment of 86 Bytes = number of Bytes to read If character set 128 is selected via command 08 "Display Mode", these 8 languages will be selected by option bits C14,C13,C12 when ESC code is inactive.
56
OSD Font Pointer
57
Display Read Column
58
User Character Set
59
User ESC Character Set
If character set 128 is selected via command 08 "Display Mode", these 8 languages will be selected by option bits C14,C13,C12 when ESC code is active.
60
Full Row Attribute
set full row attribute of specified rows without changing level 2 bit 32 Bytes are copied into mapping ram via I/O page register 0276H
61
User Mapping
Micronas
75
VCT 38xxA
3.13.I/O Register Most hardware-related functions of the TPU are controlled by memory mapped I/O of the 65C02. The application software has access to the I/O registers via I2C bus using the CPU subaddresses SUB1 and SUB2 (see Section 3.14.1.1. on page 82).
ADVANCE INFORMATION
Most of the I/O registers can only be written and will not return useful data when read by application software. Reset values are written by TPU during initialization. Note: For compatibility reasons, every undefined bit of a write register should be set to `0'. Undefined bits of a read register should be treated as "don't care".
0200 H Bit all 7 6 5 4 3 2 1 0
R/W Reset 00 H 0 0 0 0 0 0 0 0
CONTROL REGISTER Write Function Read Function
During reset the control register is loaded with the contents of the address FFF9H, but it can be read and written via software. 1 = CPU disable 0 = CPU enable 1 = program RAM disable 0 = program RAM enable 1 = program ROM disable 0 = program ROM enable 1 = character ROM disable 0 = character ROM enable 1 = DMA interface disable 0 = DMA interface enable 1 = I/O page disable 0 = I/O page enable 1 = test mode on 0 = test mode off 1 = burnin test mode (only if test pin high) 0 = normal test mode 1 = burnin test mode 0 = normal test mode
0202 H Bit 2 1
Write Reset 0 0
STANDBY Function 1 = digital circuitry power off(CPU still active with slow clock) 0 = digital circuitry power on 1 = analog front-end power off 0 = analog front-end power on
0213 H Bit 1
Write Reset 0
INTERFACE MODE Function 1 = standby enable 0 = standby disable (if bit 2 of register 0202H = 1)
0251 H Bit all
Write Reset 07 H
BLANKING STOP Function horizontal stop of blanking pulse in character increments correct blanking pulse cannot be guaranteed if blanking start = blanking stop
76
Micronas
ADVANCE INFORMATION
VCT 38xxA
0252 H Bit all
Write Reset 00 H
BLANKING START Function horizontal start of blanking pulse or self-timed HSYNC in character increments correct blanking pulse cannot be guaranteed if blanking start = blanking stop
0254 H Bit 7 6 5 4 3 to 0
Write Reset 0 1 1 0 0
DISPLAY MODE 1 Function 1 = OSD layer always uses FONT 1 0 = OSD layer changes from FONT 1 to FONT 2 if ASCII20H 1 = enable OSD layer 0 = disable OSD layer 1 = active flash phase of OSD layer 0 = inactive flash phase of OSD layer 1 = 13 scanlines/character 0 = 8 scanlines/character With this scan line the OSD layer starts display of the first text line. By slow incrementing of this value soft scroll begins.
0255 H Bit 7 3 2 1 0
Write Reset 0 1 1 0 1
DISPLAY MODE 2 Function 1 = OSD layer control code defines character set 0 = OSD layer control code defines color 1 = 10.125MHz display clock 0 = 20.25MHz display clock 1 = font pointer offset 10 scanlines/character 0 = font pointer offset 8 or 16 scanlines/character (depending on bit 1) 1 = font pointer offset 16 scanlines/character 0 = font pointer offset 8 scanlines/character 1 = 10 scanlines/character 0 = 8 or 13 scanlines/character (depending on bit 4 in register 0254 H)
025A H Bit 5 to 3 2 to 0
Write Reset 110 101
PRIO MODE Function prio code for shadow pixel prio code for normal pixel
025B H Bit all 7 6 4
R/W Reset 00 H 0 0 0
FB Mode Write Function Read Function every read resets status color bit 4(color output of OSD layer) color bit 3(color output of OSD layer) 1 = inverted color output 0 = normal color output
Micronas
77
VCT 38xxA
ADVANCE INFORMATION
0260 H Bit all
Write Reset 00 H 60 H
OSD LAYER VERTICAL START Function 9-bit value defining vertical position (in scanline) 1st write: bit 0 = MSB 2nd write: bit 7 to 0 = 8 LSBs
0261 H Bit all
Write Reset 01 H 28 H
OSD LAYER VERTICAL STOP Function 9-bit value defining vertical position (in scanline) 1st write: bit 0 = MSB 2nd write: bit 7 to 0 = 8 LSBs
0262 H Bit all
Write Reset 16 H
OSD LAYER HORIZONTAL START Function 8-bit value defining horizontal start position (in character)
0264 H Bit all
Write Reset
OSD LAYER TEXTPOINTER Function 16-bit value defining memory address of text 1st write: bit 7 to 0 = 8 MSBs 2nd write: bit 7 to 0 = 8 LSBs
-
0265 H Bit all
Write Reset 01 H 38 H
OSD LAYER 2nd COLOR START Function 9-bit value defining vertical start for 2nd color (in scanline) 1st write: bit 0 = MSB 2nd write: bit 7 to 0 = 8 LSBs
0266 H Bit 6 to 0
Write Reset 0C H
OSD LAYER 2nd COLOR Function 7-bit value defining 2nd color 2nd color is used during 1 text row (8, 10 or 13 scanlines) after 2nd color start
0267 H Bit all
Write Reset 00 H 24 H
WST LAYER VERTICAL START Function 9-bit value defining vertical position (in scanline) 1st write: bit 0 = MSB 2nd write: bit 7 to 0 = 8 LSBs
0268 H Bit all
Write Reset 0F H
WST LAYER HORIZONTAL START Function 8-bit value defining horizontal start position (in character)
78
Micronas
ADVANCE INFORMATION
VCT 38xxA
026A H Bit all
Write Reset 01 H 28 H
WST LAYER VERTICAL STOP Function 9-bit value defining vertical position (in scanline) 1st write: bit 0 = MSB 2nd write: bit 7 to 0 = 8 LSBs
026B H Bit all
Write Reset 01 H 1E H
WST LAYER LAST ROW Function 9-bit value defining last scanline of the last row to display level 1 double height after this scanline the level 1 double height attribute will not be decoded anymore 1st write: bit 0 = MSB 2nd write: bit 7 to 0 = 8 LSBs
026C H Bit 5 4 to 3
Write Reset 0 0
RGB MODE Function 1 = WST layer mixed mode 0 = WST layer normal mode 11 = WST layer top 10 = WST layer opaque bottom 01 = WST layer transparent bottom 00 = WST layer disable 1 = OSD layer mixed mode 0 = OSD layer normal mode 11 = OSD layer top 10 = OSD layer opaque bottom 01 = OSD layer transparent bottom 00 = OSD layer disable
2 1 to 0
0 0
026D H Bit 5 4
Write Reset 0 0
SYNC MODE Function 1 = double scan enable 0 = double scan disable 1 = blanking disable 0 = blanking enable
026F H Bit 7 6 5 4 3 to 0
Write Reset 1 0 0 0 FH
DISPLAY MODE 3 Function 1 = 10 pixel/character 0 = 8 pixel/character 1 = double dot size in vertical direction(OSD layer only) 0 = normal dot size in vertical direction 1 = double dot size in horizontal direction(OSD layer only) 0 = normal dot size in horizontal direction 1 = black colors replaced by transparent & shadow(OSD layer only) 0 = black colors displayed black 4-bit value defining delay of horizontal start for both layers (in pixel) delay = mod16 (character_width - 2 - value)(leftmost position should not be used!)
Micronas
79
VCT 38xxA
ADVANCE INFORMATION
0270 H Bit 4 3 2 1 0
Write Reset 0 0 0 0 0
DISPLAY MODE 4 Function 1 = new mosaic mode (single switch to character set 1) 0 = old mosaic mode (static switch to character set 1) 1 = level 1 display mode (read 40 Byte from display bank) 0 = level 2 display mode (read 86 Byte from display bank) 1 = boxing enable 0 = boxing disable 1 = reveal enable 0 = reveal disable This bit is taken as flash clock for the WST layer, the frequency should be around 6 Hz.
0273 H Bit 4 3 to 0
Write Reset 0 0
DISPLAY MODE 5 Function WST layer scan line counter preset (LSB for zoom mode) WST layer scan line counter preset
028E H Bit 4
Write Reset 0
DRAM MODE Function 1 = next CPU write without WEQ but with address increment 0 = normal CPU write mode
3
0
1 = reset address pointer and switch off refresh during standbyt 0 = keep address pointer and refresh during standby
2
1
1 = display channel enable 0 = display channel disable
1
1
1 = slicer channel enable 0 = slicer channel disable
029C H Bit 5 to 0
Read Reset
ACQ SOFT ERROR COUNTER Function 6-bit soft error counter counts number of soft error corrected bytes counter stops at 63 reset after read
-
029E H Bit 7 6
Read Reset
ACQ SYNC STATUS Function 1 = field 1 0 = field 2 1 = vertical retrace 0 = vertical window set at line 624 (PAL) or line 524 (NTSC) reset at line 313 (PAL) or line 263 (NTSC) set at line 628 (PAL) or line 528 (NTSC) reset at line 624 (PAL) or line 524 (NTSC)
- -
80
Micronas
ADVANCE INFORMATION
VCT 38xxA
029F H Bit 7 6 5 7 to 5
Write Reset 0 0 0 0
ACQ STANDARD Function 1 = CAPTION enable in field 2 0 = CAPTION disable in field 2 1 = CAPTION enable in field 1 0 = CAPTION disable in field 1 1 = VPS enable 0 = VPS disable VPS and CAPTION cannot be used at the same time, therefore these combinations are used to enable WSS reception on a PAL+ signal 0= 1 = VPS 2 = CAPTION field 1 3 = WSS & VPS 4 = CAPTION field 2 5 = WSS & VPS 6 = CAPTION field 1&2 7 = WSS 1 = acquisition enable 0 = acquisition disable 00 = PAL mode 10 = NTSC mode 11 = Caption full field mode
4 1 to 0
1 0
02A3 H Bit 1 to 0
Write Reset 0
ACQ VIDEO INPUT Function 00 = VIN1 01 = VIN2 10 = VIN3 11 = VIN4
02A4 H Bit 7 to 0
Read Reset 0
ACQ HSYNC COUNTER Function number of detected horizontal sync pulses per frame divided by 4 sync pulse is detected if within horizontal window of HPLL counter is latched with vertical sync, the register can be read at any time
Micronas
81
VCT 38xxA
3.14.I2C-Bus Slave Interface Communication between the TPU and the TV controller is done via I2C bus. For detailed information on the I2C bus please refer to the Philips manual `I2C bus Specification'. The TPU acts as a slave transmitter/receiver and uses clock synchronization to slow down the data transfer if necessary. General call address will not be acknowledged. Different memories and functions of TPU can be accessed by subaddressing. The byte following the slave address byte is defined as the subaddress byte. Maximum length of an I2C telegram is 256 Bytes following slave address and subaddress byte. The interface supports data transfer with autoincrement. The I2C bus interface is interrupt-driven and uses an internal 48-Byte buffer to collect I2C data in real-time without disturbing internal processes. This is done to avoid clock synchronization as far as possible. When the TPU has to process the I2C buffer and the I2C telegram has not yet been stopped, the I2C clock line will be held down.
ADVANCE INFORMATION
The time required to process the I2C buffer depends on other processes running inside the TPU firmware. Thus the following I2C telegram addressing the TPU can be held after the slave address byte until the old telegram is completely processed.
3.14.1.Subaddressing Access to all memory locations and to the command interface is achieved by subaddressing. Both the external DRAM and the internal CPU memory can be addressed completely. The TPU acknowledges 6 different subaddresses following the slave address (see Table 3-17 on page 82). The following symbols are used to describe the I2C example telegrams: < > ab ah al cc dd ss .. start condition stop condition address bank byte address high byte address low byte command byte data byte status byte 0 - n continuation bytes
Table 3-17: I2C bus subaddresses Name
TPU Sub 1 Sub 2 Sub 3 Sub 4 Data Status
Binary Value
0010 001x 0111 1000 0111 1001 0111 1010 0111 1011 0111 1100 0111 1101
Hex Value
22, 23 78 79 7A 7B 7C 7D
Mode
W, R W W W W R/W R
Function
TPU slave address subaddressing CPU (static) subaddressing CPU (autoincrement) subaddressing DRAM (autoincrement) subaddressing command language subaddressing data register status register bit 7 = command wait bit 6 = command invalid bit 5 = command found no data bit 4 = not used bit 3 = not used bit 2 = not used bit 1 = 0 bit 0 = 0
3.14.1.1. CPU Subaddressing There are 2 CPU subaddresses to access CPU memory: either with static memory address or with autoincrementing memory address. The main purpose of CPU subaddressing is to write text into the OSD buffer and to access the I/O page (see Section 3.13. on
page 76). The static CPU subaddress can be used to write more than 1 Byte into the same I/O page register. The CPU subaddress has to be followed by 2 address bytes defining the CPU memory address. The following data byte is written into this address. In the case of autoincrement the continuation bytes are written into incrementing memory addresses.
82
Micronas
ADVANCE INFORMATION
VCT 38xxA
3.14.1.3. Command Subaddressing TPU supports a command language, allowing the host controller to start complex processing inside the TPU with simple commands (see Section 3.12. on page 68). Commands have to be sent to the command subaddress. The command subaddress has to be followed by the command code. The following data bytes are taken as command parameters. The execution time for commands depends on other processes running inside the TPU firmware, therefore the host controller has to read the status register to get information about the running command before reading command parameter or starting other commands. The status register returns information about the command interface. The `command wait' bit is set during execution of a command and is reset when a command is executed completely and read parameters are available. If a non-existing command is sent to the TPU, the `command invalid' bit is set. If a command could not be executed successfully, the `command found no data' bit is set. In this case the read parameters of this command are not valid. Reading status from TPU is done by subaddressing the status register followed by repeated start condition and slave read address (see Fig. 3-21). < 22 7B cc dd .. > < 22 7D < 23 ss .. > < 22 7C < 23 dd .. > Telegrams subaddressing the command interface are buffered and processed after receiving the stop condition. Therefore the command code and all necessary command parameters have to be included in a single telegram.
The CPU telegram can be stopped after the 2 memory address bytes. The following I2C telegram subaddressing the data register will continue data transfer to or from the CPU memory. The data transfer will always start at the CPU memory address (autoincrement is not saved). < 22 78 ah al dd .. > < 22 79 ah al dd .. > < 22 79 ah al > < 22 7C dd .. > Data is directly written into CPU memory without using the I2C buffer of TPU and without waiting for a stop condition.
3.14.1.2. DRAM Subaddressing DRAM access is necessary to generate level 2 displays. The external DRAM can be addressed on byte level. The maximum DRAM size of 16 Mbit requires a 21-bit memory address pointer. The format of the DRAM address pointer is shown in Fig. 3-20.
5-bit Bank
8-bit High
8-bit Low
Fig. 3-20: DRAM address pointer
The DRAM subaddress has to be followed by 3 address bytes defining the DRAM address pointer. The following data byte is written into this address. DRAM subaddressing always uses autoincrement. Separate read and write DRAM address pointers are saved for autoincrement. The DRAM telegram can be stopped after the 3 address pointer bytes. The following I2C telegram subaddressing the data register will continue data transfer to or from the DRAM. When reading the DRAM, the first data byte the TPU returns is a dummy byte, which has to be ignored. < 22 7A ab ah al dd .. > < 22 7A ab ah al > < 22 7C dd .. > < 22 7A ab ah al > < 22 7C < 23 dd ..> Data written to the DRAM subaddress is collected first in the I2C buffer of TPU and is copied to DRAM when the buffer is full (48 Bytes) or after stop condition. During the time the buffer is copied to DRAM the TPU will hold the I2C clock line down. Reading data from the DRAM subaddress is also buffered internally. Reading the first byte will only empty the I2C buffer. Every time the buffer is empty, the TPU will copy 48 Bytes from DRAM into the I2C buffer. During this time the TPU will hold the I2C clock line down.
3.14.1.4. Data Subaddressing Writing data to TPU memory is possible by subaddressing the data register directly. The data is then written into memory addressed by the foregoing telegram. < 22 7C dd .. > Reading data from TPU is done by subaddressing the data register followed by a repeated start condition and slave read address (see Fig. 3-21). The returned data depend on the subaddress selected in the preceding TPU telegram. < 22 7C < 23 dd .. >
Micronas
83
VCT 38xxA
ADVANCE INFORMATION
S
0010001
W Ack
0111 1000
Ack
n Byte Sub 1
Ack
P
S
0010001
W Ack
0111 1001
Ack
n Byte Sub 2
Ack
P
S
0010001
W Ack
0111 1010
Ack
n Byte Sub 3
Ack
P
S
0010001
W Ack
0111 1011
Ack
n Byte Sub 4
Ack
P
S
0010001
W Ack
0111 1100
Ack
n Byte Data
Ack
P
S
0010001
W Ack
0111 1100
Ack
S
0010001
R
Ack
n-1 Byte Data last Byte Data
Ack Nak P
S
0010001
W Ack
0111 1101
Ack
S
0010001
R
Ack
Status Status
Ack Nak P
SDA
1 0 S P
SCL
W R Ack Nak S P
= = = = = = = =
0 1 0 1 Start Stop Interrupt Data from TPU
Fig. 3-21: I2C bus protocol
3.14.1.5. Hardware Identification A separate I2C bus slave register is reserved to read out the hardware version of VCT 38xxA. This register is active in standby mode.
I2C Sub address
Number of bits
Mode
Function
Default
Name
h'9F
16
r
Hardware version number bit[7:0] hardware id (A3=h'13, B1=h'21 a.s.o.) bit[15:8] product code VCT38xy (VCT3832=h'32)
read HWID only TC PROD
84
Micronas
ADVANCE INFORMATION
VCT 38xxA
4. Audio Processing 4.1. Introduction The audio processing allows input selection and volume control for mono audio sources either from tuner or from SCART input. 4.2. Input Select Both audio output channels can be switched to any of the three audio input channels. Only the audio output channel AOUT1 can be volume controlled.
AIN1 AIN2 AIN3 AOUT1
4.3. Volume Control The analog volume control covers a range from +18 dB and -75 dB. The lowest step is the mute position. Step size is split into a 3-dB and a 1.5-dB range.
AOUT2
-75 dB...-54 dB : 3 dB step size -54 dB...+18 dB : 1.5 dB step size
4.4. I2C-Bus Slave Interface The input selection and analog volume is controlled via the audio control register ACON. This I2C register is activated by the chip address of the video back-end processing (see Table 2-2 on page 32).
Fig. 4-1: Audio processing
Table 4-1: Audio control register
I2C Sub address Number of bits Mode Function Default Name
h'34
16
w
Audio Control bit [5:0] volume control 000000 mute 000001 -75db ... -57.0dB 000111 -54.0dB 001000 ... 101011 -1.5dB 101100 0.0dB 101101 +1.5dB ... 110110 +15.0dB 110111 +16.5dB 111000 +18.0dB bit [7:6] reserved bit [9:8] audio input select 1 00 mute 01 AIN1 10 AIN2 11 AIN3 bit [11:10] audio input select 2 00 mute 01 AIN1 10 AIN2 11 AIN3 bit[12] low power mode 0 disable low power mode 1 enable low power mode bit[15:13] reserved
0 ACON AVOL
ASEL1
ASEL2
ALPM
Micronas
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VCT 38xxA
5. TV Controller 5.1. Introduction The TV controller basically consists of the CPU, RAM, ROM, and a number of peripheral modules. For instance: - a memory banking module is included to allow access to more than 64 kB memory. - a bootloader software is included to allow in-systemdownloading of external code to Flash memory via the I2C interface. The TV controller runs the complete software necessary to control a TV set. The software includes control of the audio, video, OSD, and text processors on chip, as well, as control of external devices like tuner or stereo decoder. Communication between the TV controller and external devices is done either via I2C bus interface or via programmable port pins. The TV Controller is clocked with fOSC = fXTAL/2. 5.2. CPU The CPU is fully compatible to WDC's W65C02 microprocessor. The processor has 8-bit registers/accumulator, an 8-bit data bus, and a 16-bit address bus. For further information about the CPU core, please refer to the WDC W65C02 data sheet. 5.2.1. CPU Slow Mode
ADVANCE INFORMATION
To reduce power consumption considerably, the user can reduce the internal CPU clock frequency to 1/256 of the normal fCPU value. In this CPU Slow mode, program execution is reduced to 1/256 of the normal speed, but clocking of most other modules remains unaffected. The modules that are affected by CPU Slow mode are: 1. CPU and Interrupt Controller with all internal and external interrupts 2. RAM, ROM and DMA 3. Watchdog Some modules must not be operated during CPU Slow mode. Refer to module sections for details. After reset the CPU is in Fast mode (fCPU = fOSC). CPU Slow mode is enabled by clearing flag CPUFST in standby register SR1. The CPU clock frequency reduction to fOSC/256 will take effect after a maximum delay of 256 fOSC periods. Returning CPU to Fast mode is done by setting flag CPUFST to High. The CPU clock frequency will immediately change to its normal fOSC value. Fig. 5-1 shows the memory access signals during CPU fast and slow mode.
fast mode fOSC PH2 CCUPH2 RW WE OE
slow mode
Fig. 5-1: Memory access signals
86
Micronas
ADVANCE INFORMATION
VCT 38xxA
Table 5-2: Internal Memory Locations Addresses 000000 - 000FFF 001E00 - 001FFF 002000 - 0023FF 002400 - 019FFF 0A0000 - 0A3FFF Internal Memory
4k Program RAM I/O Register 1k Bootloader ROM 95k Program ROM 16k Text RAM
5.3. RAM and ROM On-chip RAM is composed of static RAM cells. The RAM will hold all information during reset, as long as the specified operating voltages are available. The 64PSDIP Multi Chip Module contains a 128-KByte Flash EEPROM of the ST M29W010B type. These devices exhibit electrical Byte program and block erase functions. Refer to the ST M29W010B data sheet for details.
5.3.1. Address Map The following ROM addresses are reserved and cannot be used to store program code. Table 5-1: Reserved (physical) addresses Addresses 00FFC6 - 00FFD5 00FFD6 - 00FFD7 00FFD8 - 00FFF7 00FFF8 00FFF9 00FFFA - 00FFFB 00FFFC - 00FFFD 0xFFFE - 0xFFFF Usage
Manufacturer ROM ID reserved for bootloader Interrupt Vectors reserved Control Word (during reset) NMI Vector (expanded by Interrupt Controller) Reset Vector IRQ/BRK Vector
5.3.2. Bootloader A segment of the internal ROM is reserved for bootloader code. Via this bootloader code it is possible to download additional code into the internal RAM and execute this code. The downloaded code can be used to program the external Flash EEPROM. After reset the bootloader checks the I2C bus pins SDA and SCL for a special identification sequence. If no identification sequence is detected, the bootloader starts the application program code. The bootloader checks the address FFD6/FFD7 of the external memory if there is a predefined pattern (A55Ah). If so, it starts the external application software else it starts the internal application software.
5.4. Control Register The Control Register CR serves to configure the ways, by which certain system resources are accessed during operation. The main purpose is to obtain a variable system configuration during IC test. Upon each High transition on the RESQ pin internal hardware reads data from address location 00FFF9h and stores it to the CR. The state of the TEST pin at this timepoint specifies which program storage source is accessed for this read: - With the TEST pin Low, the control byte is read from internal program storage (mask ROM). With location 00FFF9h set to FFh, this is the setting for standalone operation. - With the TEST pin High, the control byte is read from external memory via the test bus (for test purposes only).The system will thus start up according to the configuration defined in address location 00FFF9h and automatically copied to register CR.
A 16-Byte address space is reserved as "Manufacturer ROM ID". This area contains a unique ROM ID number which has to be agreed between Micronas and the customer. Especially the first 6 digits identify customer and version. As an example a Micronas demo software is identified like "MI1108 240700 TV". Table 5-2 shows the internal memory segmentation. Internal program RAM and ROM can be disabled via the Control Register (chapter 5.4. on page 87). The internal text RAM can be disabled via Standby Register 0 (see page 89). All memory locations not available internally will be addressed as external memory. It is possible to operate with internal and external memory in parallel, but overlapping memory segments will always be addressed internally. During internal memory access, the pins DB0-DB7, WExQ and OExQ are tristate. For emulation and test purposes it is possible to change this behavior via the
Micronas
87
VCT 38xxA
ADVANCE INFORMATION
1:
1F01
7 6
2:
CR
5 4 MFM
3:
Control Register
3 2 IROM 1 IRAM 0 ICPU
bit r/w reset
Table 5-5: Some commonly used settings for address location 00FFF9h. Code FFh DFh ABh TEST Pin 0 0 1 Operation Mode Stand-alone with internal ROM or Flash Emulator mode (CPGA257 package) External program storage connected to Multi Function pins in Bus mode
RESLNG TSTTOG DISEXT
TSTROM
Value of 00FFF9h
RESLNG r/w1: r/w0:
Reset Pulse Length Pulse length is 4095/fOSC. Pulse length is 16/fOSC.
This bit specifies the length of the reset pulse which is output at pin RESQ following an internal reset. If pin TEST is 1 the first reset after power on is short. The following resets are as programmed by RESLNG. If pin TEST is 0 all resets are long. TSTTOG r/w1: r/w0: TEST Pin Toggle Pin TEST can toggle the Multi Function pins. Pin TEST can't toggle the Multi Function pins.
Table 5-3: TSTROM and IROM usage in mask ROM parts TSTROM IROM 1 1 0 selected program storage internal CPU ROM internal Test ROM external on Multi Function pins in Bus mode
This bit is used for test purposes only. If TSTTOG is true in IC active mode, pin TEST can toggle the Multi Function pins between Bus mode and normal mode. DISEXT r/w1: Disable External Memory Access DB0-DB7, WExQ and OExQ output pins are tristate during internal memory access (see Fig. 5-2 on page 89). DB0-DB7, WExQ and OExQ output pins are active during internal memory access. Multi Function pin Mode Enable normal mode. Enable Test Bus mode. Test ROM (mask ROM parts only) Disable internal Test ROM. Enable internal Test ROM (@ IROM=1). Internal ROM Enable internal CPU ROM. Disable internal CPU ROM. Internal RAM Enable internal CPU RAM. Disable internal CPU RAM. Internal CPU Enable internal CPU. Disable internal CPU.
1 0 x
r/w0:
Table 5-4: TSTTOG and MFM usage TSTTOG MFM TEST pin Multi Function Pins normal mode normal mode Bus mode Bus mode
MFM r/w1: r/w0: TSTROM r/w1: r/w0: IROM r/w1: r/w0: IRAM r/w1: r/w0: ICPU r/w1: r/w0:
x 1 1 0
1 0 0 0
x 1 0 x
88
Micronas
ADVANCE INFORMATION
VCT 38xxA
PH2 RW ADB DB OE WE DB OE WE Fig. 5-2: Internal/external memory access 5.5. Standby Registers The Standby registers allow the user to switch on/off power or clock supply of single modules. With these flags it is possible to greatly influence power consumption and its related electromagnetic interference. For details about enabling and disabling procedures and the standby state refer to the specific module descriptions. The minimum IC current consumption is obtained with all standby registers set to 00h.
bit r/w
internal signal internal signal extern extern intern intern
Controlword DISEXT= 1
Controlword DISEXT= 0
CCC r/w1: r/w0: TVPWM r/w1: r/w0:
Capture Compare Counter Module active. Module off. Tuning Voltage Pulse Width Modulator Module active. Module off.
7:
1F09
7 6
8:
SR1
5 4
9:
Standby Register 1
3 ADC 2 1 TIM1 0 0 0 TIM0 0
CPUFST 0 1 0 0
4:
1F08
7 6
5:
SR0
5 PWM0 0 0 4
6:
Standby Register 0
3 2 TRAM 0 0 1 CCC 0 0 TVPWM 0
reset
0
bit r/w reset
PWM1 0 0
CPUFST r/w1: r/w0: ADC r/w1: r/w0: TIM1 r/w1: r/w0: TIM0 r/w1: r/w0:
CPU Fast Mode Fast mode: fCPU = fXTAL / 2 Slow mode: fCPU = fXTAL / 512 ADC Module Module active. Module off. Timer 1 Module active. Module off. Timer 0 Module active. Module off.
PWM1 r/w1: r/w0: PWM0 r/w1: r/w0: TRAM r/w1: r/w0:
Pulse Width Modulator 1 Module active. Module off. Pulse Width Modulator 0 Module active. Module off. Text RAM Module active Module off
Micronas
89
VCT 38xxA
ADVANCE INFORMATION
10:
1F0A
7 6
11:
SR2
5 PWM2 0 0 4
12:
Standby Register 2
3 2 I2C 0 0 0 1 0 MB 0
22:
1FFC
7 6
23:
TST4
5 4
24:
Test Register 4
2 1 0
bit r/w reset
bit w reset
3
PWM3 0 0
For testing purposes only 0 0 0 0 0 0 0 0
PWM3 r/w1: r/w0: PWM2 r/w1: r/w0: I2C r/w1: r/w0: MB r/w1: r/w0:
Pulse Width Modulator 3 Module active. Module off. Pulse Width Modulator 2 Module active. Module off. I2C-Bus Master Interface Module active. Module off. Memory Banking Module active. Module off.
25:
1FFB
7 6
26:
TST5
5 4
27:
Test Register 5
2 1 0
bit r reset
3
For testing purposes only 0 0 0 0 0 0 0 0
5.7. Reset Logic 5.7.1. Alarm Function An alarm comparator on the pin RESQ allows the detection of a threshold higher than the reset threshold. An alarm interrupt can be triggered with the output of this comparator. The interrupt source output of this module is routed to the Interrupt Controller logic. But this does not necessarily select it as input to the Interrupt Controller. Check section "Interrupt Controller" for the actually selectable sources and how to select them. The intended use of this function is made, when a system uses a 3.3V regulator with an unregulated input. In this case, the unregulated input, scaled down by a resistive divider, is fed to the RESQ pin. With falling regulator input voltage this alarm interrupt is triggered first. Then the reset threshold is reached and VCT 38xxA is reset before the regulator drops out. The time interval between the occurrence of the alarm interrupt and the reset may be used to save process data to nonvolatile memory. In addition, power saving steps like turning off other devices may be taken to increase the time interval until reset. The alarm interrupt is a level triggered interrupt. The interrupt is active as long as the voltage on pin RESQ remains between the two thresholds of alarm and reset (see Fig. 5-3 on page 92).
5.6. Test Registers Test registers are for manufacturing test only. They must not be written by the user with values other than their reset values (00h). They are valid independent of the TEST input state. In all applications where a hardware reset may not occur over long times, it is good practice to force a software reset on these registers within appropriate intervals.
13:
1FFE
7 6
14:
TST1
5 4
15:
Test Register 1
2 1 0
bit w reset
3
For testing purposes only 0 0 0 0 0 0 0 0
16:
1FFF
7 6
17:
TST2
5 4
18:
Test Register 2
2 1 0
bit w reset
3
For testing purposes only 0 0 0 0 0 0 0 0
5.7.2. Software Reset The TV controller software can generate a reset via the Reset Control Register (see page 94). To prevent the TV controller from carrying out a reset in this case, the internal CPU reset can be disconnected from the RESQ pin.
19:
1FFD
7 6
20:
TST3
5 4
21:
Test Register 3
2 1 0
bit w reset
3
For testing purposes only 0 0 0 0 0 0 0 0
90
Micronas
ADVANCE INFORMATION
VCT 38xxA
5.7.2.1. From Standby into Normal Mode To switch the whole TV application from standby operation into normal mode the controller has to perform the following sequence: - RC.RESDIS = 1, RC.DCOCLP = 1 - RC.RESOUT =1 - switch on power supply - wait for stable power supply - RC.SELCLK = 1, RC.I2CEN = 1 - RC.DCOCLP = 0, RC.RESOUT = 0 - wait for RC.ALI = 0 (ext. capacitor!) - RC.RESDIS = 0 - init DMA interface - init TPU, VDP and Audio - init external devices
5.7.2.2. From Normal into Standby Mode To switch the whole TV application from normal mode into standby operation the controller has to perform the following sequence: - RC.DCOCLP = 1, RC.I2CEN = 0 - wait 1ms for stable 20.25MHz DCO - RC.SELCLK = 0 - turn off power supply - set TPU into standby mode - SR0 = 2, SR1 = 8, SR2 = 0
5.7.3. Internal Reset Sources The VCT 38xxA contains three internal circuits that are able to generate a system reset: watchdog, supply supervision, and clock supervision. All internal resets are directed to the open drain output of pin RESQ. Thus a "wired or" combination with external reset sources is possible. The RESQ pin is current limited and therefore large external capacitances may be connected. All internal reset sources initially set a reset request flag. This flag activates the pull-down transistor on the RESQ pin. An internal reset prolongation counter starts, as soon as no internal reset source is active any more. It counts 4096 fCPU periods (for alternative settings refer to register CR) and then resets the reset request flag, thus releasing the RESQ pin.
Micronas
91
VCT 38xxA
ADVANCE INFORMATION
RC.VSI Bandgap VREFA VREFR VREFPOR
Voltage Supervision TPU Watchdog
VSUPD
RESET Interrupt Source
internal Reset to DMA, TPU, VDP
>1
RC.TPUI
RC.ALI
VREFA
CPU Reset
>1
RC.RESDIS RC.RESOUT
Watchdog >1 VREFPOR VSUPS + Clock Supervision CSW0.CSA
SQ R
>1
>1 & RC
&
Reset extension 16 or 4096 oscillator pulses
>1
Fig. 5-3: Block diagram of reset logic
5.7.3.1. Supply Supervision An internal bandgap reference voltage is compared to VSUPS. A VSUPS level below the Supply Supervision threshold VREFPOR will permanently pull the pin RESQ low and thus hold the VCT 38xxA in reset state (see Fig. 5-3 on page 92). This reset source is active after reset and can be enabled/disabled by flag CSA in register CSW0.
5.7.3.2. Clock Supervision The Clock Supervision monitors the CPU clock frequency fCPU. A frequency level below the clock supervision threshold of approx. 200 kHz will permanently pull the pin RESQ low and thus hold the IC in reset (see Fig. 5-3 on page 92). This reset source is active after reset and can be enabled/disabled by flag CSA in register CSW0. A frequency exceeding the specified clock frequency is not detected.
92
+ +
reset
VREFR
RESQ
Reset Control
Micronas
ADVANCE INFORMATION
VCT 38xxA
5.7.3.3. Watchdog The Watchdog module serves to monitor undisturbed program execution. A failure of the program to retrigger the Watchdog within a preselectable time will pull the RESQ pin low and thus reset the VCT 38xxA (see Fig. 5-3 and Fig. 5-4). The Watchdog reset source is only enabled after the first write access to register CSW1 (see Section 5.7.3.2. on page 92). Once the Watchdog is enabled, it cannot be disabled anymore, neither by software nor by pulling down the external RESQ pin. Only after power up the watchdog is disabled.
2.write & even
CSW1 Trigger Reg1
8
3.write & odd
CSW1 Trigger Reg2
8
CSW1
1. write
Timer Register
8
clk = fCPU/8192 1. write
=
& &
1
load
8-Bit-Counter
zero
2.write & even 3.write & odd reset in
1
DQ C S
1. write
SQ R
&
SQ R
reset out
power on write CSW1
CSW1.WDRES
1
Fig. 5-4: Block diagram of watchdog
The Watchdog contains a down-counter that generates a reset when it wraps from zero to FFh. It is reloaded with the content of the watchdog timer register, when, on a write access to register CSW1, watchdog trigger registers 1 and 2 contain bit complemented values. Resetting the VCT 38xxA initializes the watchdog timer register to FFh, thus forcing the Watchdog to create a maximum reset interval. The Watchdog is controlled by register CSW1. The first write access to it loads the timer register value setting the Watchdog's unretriggered reset interval. The desired interval can be programmed by setting the CSW1 value to:
Interval x f CPU Value = ----------------------------------- - 1 8192
The resolution of the Watchdog is 8192/fCPU. In CPU Slow mode (see Section 5.2.1. on page 86), the watchdog is clocked with the reduced CPU clock. The second and all following even numbered write accesses load watchdog trigger register 1, the third and all following odd numbered write accesses load watchdog trigger register 2. In all future, the CPU has to write alternatingly to register CSW1 value and bit complement value, thus retriggering the up-counter. Failure to retrigger will result in an overflow of the up-counter generating a Watchdog reset. It is not allowed to change a chosen value. Writing a wrong value to CSW1 immediately sets the flag CSW1.WDRES and prohibits further retriggering of the watchdog counter. CSW1.WDRES is true after a Watchdog reset. Only a Supply Supervision reset or a write access to register CSW1 clears it.
Micronas
93
VCT 38xxA
5.7.4. External Reset Sources As long as the reset input comparator on the pin RESQ detects the Low level, the VCT 38xxA is in reset state. On this pin, external reset sources may be wireored with the internal reset sources, leading to a system-wide reset signal combining all system reset sources.
ADVANCE INFORMATION
If the source of one of these interrupts is still active, resetting the interrupt flag will not work and no further interrupt will be generated. I2CEN r/w1: r/w0: DCOCLP r/w1: r/w0: SELCLK r/w1: r/w0: RESDIS r/w1: r/w0: RESOUT w1: w0: I2C Enable Enable I2C output from FE/BE. Disable I2C output. DCO clamping DCO input clamped to 0. DCO input controlled by front-end. Select clock source From PLL. From DCO. Reset Disable Disable internal CPU reset. Enable internal CPU reset. RESQ Output RESQ output active. RESQ output inactive.
5.7.5. Summary of Module Reset States After reset, the controller modules are set to the following reset states: Table 5-6: Status after reset Module CPU Interrupt Controller Ports Watchdog Clock monitor Status CPU Fast mode. Interrupts are disabled. Priority registers, request flip-flops and stack are cleared. Normal mode. Output is tristate.
31:
1F00
7 x x
32:
CSW0
5 x x
33:
Switched off. SW activation is possible. EMU IC: Active. SW may toggle. normal IC: Permanently active.
Clock, Supply & Watchdog Register 0
4 x x 3 x x 2 x x 1 x x 0 CSA 1
bit w reset
6 x x
This register controls the Supply and Clock Supervision modules. 5.7.6. Reset Registers
28:
1F07
7 ALI ALI 0 6 VSI VSI 0
29:
RC
5 TPUI TPUI 0 4
30:
Reset Control Register
3 2 1 0
bit w r reset
CSA w1: w0:
Clock and Supply Supervision Active Both Enabled. Both Disabled.
I2CEN DCOCLP SELCLK RESDIS RESOUT I2CEN DCOCLP SELCLK RESDIS 0 1 0 0 0 0
34:
1F60
7 x
35:
CSW1
5 x
36:
Clock, Supply & Watchdog Register 1
4 x 3 x 2 x 1 x 0 WDRES
This register controls the reset logic and clock generation. ALI r1: r0: w1: VSI r1: r0: w1: TPUI r1: r0: w1: Alarm Interrupt Alarm was interrupt source no pending alarm interrupt reset alarm interrupt VSUPD Voltage Supervision Interrupt VSUPD supervision was interrupt source no pending VSUPD supervision interrupt reset VSUPD supervision interrupt TPU Watchdog Interrupt TPU watchdog was interrupt source no pending TPU watchdog interrupt reset TPU interrupt flag
bit r w reset
6 x
Watchdog Time and Trigger Value 1 1 1 1 1 1 1 1
This register controls the Watchdog module. Only values between 1 and 255 are allowed. WDRES r1: w: Watchdog Reset Source Watchdog was reset source. Any write access to CSW1 resets this flag.
First write the desired watchdog time value to this register. On further writes, to retrigger the Watchdog, alternatingly write a value (not necessarily the former time value) and its bit complemented value. Never change the latter value.
94
Micronas
ADVANCE INFORMATION
VCT 38xxA
5.8. Memory Banking
*D0 ... D7
Banking Register
A15 ... A19
A15 ... A19
65C02
*A15 *A0 ... A14 *Processor internal Bus
Interrupt Controller, DMA Logic
A0 ... A14
Address Decoder, Memory, I/O
A0 ... A14
Fig. 5-5: Block diagram of Memory Banking
The 8-bit processor W65C02 only allows access to 64 kByte of memory space. To allow access to the expanded memory range above 64 kByte, a specific banking hardware is implemented. The physical address range above 32 kBytes (A15 = 1) is separated into several banks of which only one at a time is enabled and selected by the Banking register (BR), which is programmable as any other standard peripheral register by writing the desired value into its specific address. The content of the BR is also readable, so the software may check the current bank at any time. The applied software is responsible to program the BR with the correct bank number at the right time. Since the upper 32 kBytes range is switched immediately after programming the BR, correct function is not guaranteed if it is changed by a program sequence running in a switched bank. BR settings need to be done in the lower 32 kBytes (A15 = 0), which is the non-switchable master bank (bank 0). Setting BN = 0 should be avoided because it will mirror the non-switchable master bank (bank 0) into the upper 32-kByte area (A15 = 1). RAM, I/O pages and reserved addresses may be manipulated unintentionally. RESET initializes BN = 1 to read control byte and reset vector from bank 1. Also, interrupt vectors have to reside in bank 1, because the Interrupt Controller generates the appropriate address of bank 1, but it does not change the contents of the BR. Interrupt functions have to reside in the non-switchable master bank (bank 0). Otherwise,they need to be in each used bank, because after getting the vector the unchanged contents of the BR determine the current bank which is valid if A15 is "1".
5.8.1. Banking Register
37:
1F0F
7 6
38:
BR
5 4
39:
Banking Register
3 2 BN 1 0
bit r/w reset
0
0
0
0
0
0
0
1
BN r/w:
Bank Number number of 32 kByte memory bank
Micronas
95
VCT 38xxA
ADVANCE INFORMATION
CPU RAM/ROM
Text RAM
TPU Address Space
128k Text RAM
19k Text RAM 000000H 16k Text RAM 000000H
000000H 000FFFH reserved 001E00H 002000H
0F8000H 0A8000H 0A0000H 088000H
000000H
Page Table
001000H
Page Table
001000H
Page Table
001000H
Bank 1 Bank 0 Bank 2 Bank 3 Bank 4 Bank 5-14 Bank 15 Bank 16 Bank 17-19 Bank 20 Bank 21-30 Bank 31
080000H
Scratch DMA Scratch
002000H 001800H
Scratch
001800H
078000H
TTX Bank
003000H
Page Memory
Page Memory
003000H
084000H
008000H
OSD Bank
16kbyte 004000H 004000H
OSD&TTX Bank OSD&TTX Bank
087FFFH
Page Memory
128kbyte 020000H
256kbyte 00FFFFH
040000H 07FFFFH
512kbyte
int. ROM
ext. ROM
int. RAM
ext. RAM
I/O-Reg
Fig. 5-6: Memory Banking shown with the maximal size of addressable memory
5.9. DMA Interface The DMA interface connects the TPU SRAM interface to the CPU memory bus (see Fig. 5-7). This is done to avoid extra pins for external TPU page memory. The DMA interface must not be operated during CPU Slow mode. The DMA interface can be disabled via DMAIM.DMAEN. As long as the DMA interface is disabled, the TPU cannot access the CPU address bus and therefore should not transfer data to/from the internal/external SRAM. To ensure this, the controller should reset the TPU before disabling the DMA interface. After reset the TPU will not access the memory until receiving the I2C command "DRAM_MODE" (see Section 3.12. on page 68).
96
Micronas
ADVANCE INFORMATION
VCT 38xxA
A[18:0] TPU SRAM Interface D[7:0] RWQ
Address Mapping
PH2 RWQ RDY BE CPU
DMA Interface
RWQ
DB[7:0]
ADB[19:0]
Fig. 5-7: Block diagram of DMA interface
In general, all TPU addresses are mapped into bank 16 to 31 of the CPU address space by forcing the MSB of the address bus to "1" (see Fig. 5-8). Additionally 4 memory segments can be mapped into any address area by programming a set of DMA registers (see Fig. 5-9).
Special care should be taken when mapping TPU addresses into the RAM area of bank 0. Any overlap between TPU memory (e.g. OSD Bank) and controller memory (e.g. non zero page variables) must be avoided.
A[18:8] A19 = "1"
TPU Address Bus map 4 map 3 map 2 map 1 12 12 12 12 12 match4 match3 match2 match1
Mux 1:5
3
Decoder
12 ADB[19:8] Fig. 5-8: DMA address mapping
Micronas
97
VCT 38xxA
If the mapping logic does not find any address match, the TPU address is directly put on the CPU address bus with A19 set to "1". In case of multiple matches, the priority is map1 > map2 > map3 > map4.
ADVANCE INFORMATION
76:
1E0C 1E0D 1E0E 1E0F
7
77:
CMP1H CMP2H CMP3H CMP4H
5 4
78:
Compare 1 High Byte Compare 2 High Byte Compare 3 High Byte Compare 4 High Byte
3 CA19 1 2 CA18 1 1 CA17 1 0 CA16 1
79:
80:
81:
82:
83:
84:
85:
86:
87:
CMP n
12 = 12 & match
bit w reset
6
A[19:8]
CA19 to 8 Compare Address Masked TPU address is compared with this value.
MASK n
12 & 1
A[19:8]
88:
1E10 1E11 1E12 1E13
7 MPA15 1
89:
MAP1L MAP2L MAP3L MAP4L
5 MPA13 1 4 MPA12 1
90:
Map 1 Low Byte Map 2 Low Byte Map 3 Low Byte Map 4 Low Byte
2 MPA10 1 1 MPA9 1 0 MPA8 1
91:
92:
93:
94:
95:
96:
MAP n
12
&
w
97:
98:
99:
bit
6 MPA14 1
3 MPA11 1
n: mapping logic 1 to 4
reset
Fig. 5-9: DMA mapping logic
100: 103:
1E14 1E15 1E16 1E17
7
101:
MAP1H MAP2H MAP3H MAP4H
5 4
102:
Map 1 High Byte Map 2 High Byte Map 3 High Byte Map 4 High Byte
3 2 MPA18 1 1 MPA17 1 0 MPA16 1
104:
105:
5.9.1. DMA Registers
106:
107:
108:
109:
110:
111:
bit
40:
6
1E00 1E01 1E02 1E03
7 MA15 1
41:
MASK1L MASK2L MASK3L MASK4L
5 MA13 1 4 MA12 1
42:
Mask 1 Low Byte Mask 2 Low Byte Mask 3 Low Byte Mask 4 Low Byte
3 2 MA10 1 1 MA9 1 0 MA8 1
w reset
MPA19 1
43:
44:
45:
46:
47:
48:
49:
50:
51:
MPA19 to 8 Map Address Matching TPU address is replaced with this value.
bit w reset
6 MA14 1
MA11 1
112:
1E18
7 DMAEN 0
113:
DMAIM
5 4
114:
DMA Interface Mode
3 2 MAP3E 0 1 MAP2E 0 0 MAP1E 0
bit
52:
6
1E04 1E05 1E06 1E07
7
53:
MASK1H MASK2H MASK3H MASK4H
6 5 4
54:
Mask 1 High Byte Mask 2 High Byte Mask 3 High Byte Mask 4 High Byte
3 2 MA18 1 1 MA17 1 0 MA16 1
w reset
MAP4E 0
55:
56:
57:
58:
59:
60:
61:
62:
63:
bit w reset
DMAEN w1: w0: MAPxE w1: w0:
DMA Enable Enable DMA Interface Disable DMA Interface Mapping Logic x Enable Enable mapping logic x Disable mapping logic x
MA19 1
MA19 to 8 Mask Address TPU address is masked with this value.
64:
1E08 1E09
65:
CMP1L CMP2L CMP3L CMP4L
5 CA13 1 4 CA12 1
66:
Compare 1 Low Byte Compare 2 Low Byte Compare 3 Low Byte Compare 4 Low Byte
3 CA11 1 2 CA10 1 1 CA9 1 0 CA8 1
67:
68:
69:
70:
1E0A 1E0B
7 CA15 1
71:
72:
73:
74:
75:
bit w reset
6 CA14 1
98
Micronas
ADVANCE INFORMATION
VCT 38xxA
operates with the new vector of the interrupt service routine. When the Interrupt Controller writes the new vector to the address bus, the interrupt pending flag of this vector is set, indicating that no interrupt is pending. The software must pull the top entry from the priority stack at the end of an interrupt service routine. This happens with the write access to the interrupt return register IRRET. Then the next entry (with lower priority) is visible at top of stack and is compared with the priority latch. The Interrupt Controller and related circuitry is clocked by the CPU clock and participates in CPU Fast and Slow mode.
5.10.Interrupt Controller The Interrupt Controller has 16 input channels (see Fig. 5-10 on page 100). Each input has its own interrupt vector pointing to an interrupt service routine (ISR). One of 15 priority levels can be assigned to each input or the input can be disabled. The Interrupt Controller is connected to the NMI input of the CPU. But despite of the non-maskable interrupt input, it is possible to disable all interrupt sources in total in the Interrupt Controller.
5.10.1.Features - 16 interrupt inputs. - 16 interrupt vectors. - 15 individual priority levels. - Global/individual disable of interrupts. - Single interrupt service mode. 5.10.3.Initialization After reset, all internal registers are cleared but the Interrupt Controller is active. When an interrupt request arrives, it will be stored in the respective pending register IRP/IRRET. But it will not trigger an interrupt as long as its interrupt priority register IRPRIxy is set to zero. Proper SW configuration of the interrupt sources in peripheral modules has to be made prior to operation. Before enabling individual inputs, make sure that no previously received signal on that input has cleared its pending flag which may trigger the Interrupt Controller. Clear all pending interrupts with the flag IRC.CLEAR to avoid such an effect.
5.10.2.General Interrupt requests are served in the order of their programmed priority level. Interrupt requests of the same priority level are served in descending order of interrupt input number. Each of the 16 interrupt inputs clears a flag in the interrupt pending register (IRRET and IRP), which can be read by the user. A pending interrupt enables the output of the corresponding priority register (IRPRI10 to IRPRIFE) which is connected to a parallel priority decoder together with the other priority registers. The decoder outputs the highest priority and its input number to a latch. The latched priority is compared with the top entry of the priority stack. The top entry of the priority stack contains the priority of the actual served interrupt. Lower entries contain interrupts with lower priority whose interrupt service routines were started but interrupted by the higher priority interrupts above. If the latched priority is lower or equal than the top of stack priority, nothing happens. If the latched priority is higher than the top of stack priority, a NMI is sent to the CPU and the latched priority is pushed on the stack. The Interrupt Controller signals an interrupt by NMI input to the CPU. After the current instruction is finished the CPU starts an interrupt sequence. First it puts the program bank register, the program counter High byte, the program counter Low byte and the program status register to the stack. Then the CPU writes the vector address Low byte (00FFFAh) to the bus. The Interrupt Controller recognizes this address and stops the CPU by the RDY signal. Now the Interrupt Controller writes the vector address Low and High byte of the corresponding interrupt number to the bus and releases the CPU by releasing RDY. The CPU now
5.10.4.Operation Activation of an interrupt input is done by writing a priority value ranging from 1h to Fh to the respective IRPRIxy register. Upon an interrupt request, pending or fresh, the Interrupt Controller will immediately generate an interrupt. During operation, changes in the priority register setting may be made to obtain varying interrupt servicing strategies. Flags IRC.DAINT, IRC.DINT and IRC.A1INT allow some variation in the Interrupt Controller response behavior.
5.10.5.Inactivation There are two possibilities to disable an interrupt within the Interrupt Controller. Changing the priority of an interrupt input to zero disables this interrupt locally. Interrupts are globally disabled by writing a zero to flag IRC.DINT of register IRC.
Micronas
99
100
Pending Register Int-Input 1 Priority Registers IRPRI10 R S Int-Input 2 R S push IRPRI32 Int-Input 3 R S Int-Input 4 R S Q Q 4 Priority Stack 15 x 4 & NMI Q Q 4 prio clke 4 priority 4 input # 4 Priority Latch clke CCUNMI CCUNMIDIS A B 4 A>B pull IRRET write 4 Parallel Priority Decoder clke DMAE RDY Ctrl 00FFFA IRPRIFE Int-Input 15 R S Int-Input 16 R S 16 Clear Request PATCH DMAE Ph2 & clke Q Interrupt Vector Table 16 enable Q 4 A B A=B A0...A23 4
VCT 38xxA
ADVANCE INFORMATION
Micronas
Fig. 5-10: Block diagram of interrupt logic
ADVANCE INFORMATION
VCT 38xxA
5.10.7.Interrupt Registers
Within the evaluation period (see Section 5.10.10. on page 106) it's not possible to suppress an interrupt by changing priority. A zero in the flag IRC.DINT of register IRC prevents the Interrupt Controller from pulling the signal NMI Low. However, if this flag is set after the falling edge of NMI, the corresponding interrupt cannot be cancelled.
115:
1F20
7 x x 6 x x
116:
IRC
5 x x 4 x
117:
Interrupt Control Register
3 DAINT DAINT 1 2 DINT DINT 1 1 x A1INT x 0 x CLEAR x
bit r w reset
RESET x
5.10.6.Precautions The write access to the IRRET must be performed just before the RTI command at the end of the interrupt service routine. After a write access to this location it is guaranteed that the next command (should be RTI) will be processed completely before a new interrupt request is signaled to the CPU. If the RTI command does not immediately follow the write to IRRET, an interrupt with the same priority may be detected before the corresponding RTI is processed. A stack underflow may occur because this may happen several times. If an opcode fetch of a disable interrupt instruction (DI) happens one clock cycle after the falling edge of NMI (see Section 5.10.10. on page 106), it is possible, that an interrupt service routine (ISR) is active, though the corresponding interrupt is disabled. That is why after disabling an interrupt, and before accessing critical data, at least one uncritical instruction is necessary. This guarantees that the ISR is finished before critical data access and no further ISR can interrupt it. Because it is now possible that an ISR can lengthen the time between DI and enable interrupt (EI) indefinitely, it is necessary that an ISR first saves registers and enables interrupt flags, and then enables interrupts. After interrupt execution, enable flags and registers must be restored. This guarantees, that other interrupts are not locked out during interrupt execution.
RESET w1: w0:
Reset No action. Momentary reset of the Interrupt Controller, all internal registers are cleared.
The reset of the Interrupt Controller happens with writing zero to this flag. It is not necessary to write a one to finish the reset. The standard interrupt controller function is performed by setting all flags to one. A hardware reset of the Interrupt Controller is performed by setting the RESET flag to Low and the other flags to High. DAINT r1: r0: w1: w0: Disable after interrupt Don't disable after interrupt. Disable Interrupt Controller after interrupt. Cancel this feature. Disable Interrupt Controller after interrupt.
This is the enable flag for the flag A1INT function. DINT r1: r0: w1: w0: A1INT w1: w0: Disable interrupt Interrupts are enabled. All interrupts are disabled. Enable interrupts according to priority setting. Disable all interrupts. Allow one interrupt No action. Serve one interrupt.
Save Registers
This is a momentary signal. With DAINT = 0, only one interrupt (with the highest priority) will be served. The Flags DAINT and A1INT must be considered in common. They provide the possibility to serve interrupts one by one, only when the main program has enough time. CLEAR w1: w0: Clear all requests No action. Momentarily clears all interrupt requests.
Execute Interrupt
Restore Registers
Write to IRRET
RTI
Fig. 5-11: Interrupt service routine
Micronas
101
VCT 38xxA
Table 5-7: Single interrupt service
133:
ADVANCE INFORMATION
1F26
7
134:
IRPRI98
5 PRIO9
135:
DAINT 0 0 1
A1INT 1 0 x
Resulting Function
bit 6
Interrupt Priority Register, Input 8 and 9
4 3 2 PRIO8 1 0
Disable after current interrupt. Serve one interrupt request. Normal interrupt mode.
r/w reset 0 0
0
0
0
0
0
0
136:
1F27
7
137:
IRPRIBA
5 PRIO11
138:
Interrupt Priority Register, Input 10 and 11
4 3 2 PRIO10 1 0
bit r/w
118:
6
1F21
7 IPF7
119:
IRRET
5 IPF5 4
120:
Interrupt Return Register
3 IPF3 2 IPF2 1 IPF1 0 IPF0
reset
0
0
0
0
0
0
0
0
bit r w reset
6 IPF6
IPF4
A write access signals the Interrupt Controller that the current request has been served. 0 0 0 0 0 0 0 0
139:
1F28
7
140:
IRPRIDC
5 PRIO13
141:
Interrupt Priority Register, Input 12 and 13
4 3 2 PRIO12 1 0
bit r/w reset
6
IPF0 to 7 r1: r0: w:
Interrupt Pending Flag of Input 0 to 7 No interrupt is pending. Interrupt is pending. Current request is finished.
0
0
0
0
0
0
0
0
142:
1F29
7
143:
IRPRIFE
5 PRIO15
144:
Interrupt Priority Register, Input 14 and 15
4 3 2 PRIO14 1 0
For interrupt pending flags 8 to 15 refer to description of register IRP. A write access to this memory location signals to the Interrupt Controller that the current request has been served.
bit r/w reset
6
0
0
0
0
0
0
0
0
PRIOn r: w:
121:
1F22
7
122:
IRPRI10
5 PRIO1
123:
Interrupt Priority Register, Input 0 and 1
4 3 2 PRIO0 1 0
Priority of interrupt input n Priority of the corresponding interrupt input. Priority of the corresponding interrupt input.
bit r/w reset
6
0
0
0
0
0
0
0
0
Priority zero prevents the Interrupt Controller from being triggered but the pending register is not affected. All incoming requests are stored in the pending registers. With two inputs having the same PRIO setting, the higher numbered input has priority. Table 5-8: PRIOn usage PRIOn
0h
124:
1F23
7
125:
IRPRI32
5 PRIO3
126:
Interrupt Priority Register, Input 2 and 3
4 3 2 PRIO2 1 0
bit r/w reset
6
0
0
0
0
0
0
0
0
Resulting Function
Interrupt input is disabled Interrupt input is enabled with lowest priority : Interrupt input is enabled with highest priority
127:
1F24
7
128:
IRPRI54
5 PRIO5
129:
Interrupt Priority Register, Input 4 and 5
4 3 2 PRIO4 1 0
1h : Fh
bit r/w reset
6
0
0
0
0
0
0
0
0
130:
1F25
7
131:
IRPRI76
5 PRIO7
132:
Interrupt Priority Register, Input 6 and 7
4 3 2 PRIO6 1 0
bit r/w reset
6
0
0
0
0
0
0
0
0
102
Micronas
ADVANCE INFORMATION
VCT 38xxA
The source can be any of the 15 special input ports (see Section 5.18.1. on page 126). The multiplexers are configured by registers IRPMUX0 and IRPMUX1.
145:
1F2A
7 IPF15 0 6
146:
IRP
5 IPF13 0 4
147:
Interrupt Pending Register
3 IPF11 0 2 IPF10 0 1 IPF9 0 0 IPF8 0
bit r reset
IPF14 0
IPF12 0
IPF8 to 15 Interrupt Pending Flag of Input 8 to 15 r1: No interrupt is pending. r0: Interrupt is pending. For interrupt pending flags 0 to 7 refer to description of register IRRET.
5.10.8.Interrupt Assignment While most interrupt assignments are hard-wired, some can be configured by software (see Fig. 5-12 on page 104). Table 5-9: Interrupt assignment Interrupt Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Interrupt Vector Address 00FFF6-F7 00FFF4-F5 00FFF2-F3 00FFF0-F1 00FFEE-EF 00FFEC-ED 00FFEA-EB 00FFE8-E9 00FFE6-E7 00FFE4-E5 00FFE2-E3 00FFE0-E1 00FFDE-DF 00FFDC-DD 00FFDA-DB 00FFD8-D9 Interrupt Source I2C T0 T1 CCCOFL CC0OR CC0COMP CC1OR CC1COMP TVPWM VSYNC RESET CMPO PINT0 PINT1 PINT2 PINT3
5.10.8.1. Interrupt Multiplexer Interrupt inputs 0-11 are directly connected to the respective module's interrupt output. Four interrupt inputs 12 to 15 allow source selection via multiplexers.
Micronas
103
VCT 38xxA
ADVANCE INFORMATION
12
Interrupt sources of peripheral modules
IRPM0
PINT0 Interrupt Controller
IRPP.P0INT4 0 1/4 Mux 0
1 IRPP.P1INT32 PINT1
Trigger Mode
0 Mux 1 1 1/32 Mux 2
15
Special Input Ports
PINT2
PINT3
Mux 3
Fig. 5-12: Interrupt assignment and multiplexer
5.10.9.Port Interrupt Module Port interrupts are the interface of the Interrupt Controller to the external world. Four port pins are connected to the module via their special input lines. Port interrupt 0 and 1 can scale down the interrupt load by prescalers. Port interrupt 2 and 3 are directly connected to the special input multiplexer. The user can define the trigger mode for each port interrupt by the interrupt port mode register. The Port interrupt prescaler can be switched by the interrupt port prescaler register. The pulse duty factor of the prescaler output is 50 %. The Trigger mode defines on which edge of the interrupt source signal the Interrupt Controller is triggered. The triggering of the Interrupt Controller is shown in Fig. 5-13 and Fig. 5-14 for port prescaler active (P1INT32 or P0INT4 = 1).
Table 5-10: PITn usage PITn 0h 1h 2h 3h Trigger Mode Interrupt source is disabled Rising edge Falling edge Rising and falling edges
151:
1F2C
7 x 6 x
152:
IRPP
5 x 4 x
153:
Interrupt Port Prescaler
3 x 2 x 1 0 P1INT32 P0INT4 0 0
bit w reset
P1INT32 w1: w0: P0INT4 w1: w0:
Port 1 interrupt prescaler Indirect mode, 1:32 prescaler Direct mode, bypass prescaler Port 0 interrupt prescaler Indirect mode, 1:4 prescaler Direct mode, bypass prescaler
148:
1F2B
7 PIT3 0
149:
IRPM0
5 PIT2 4
150:
Interrupt Port Mode
3 PIT1 2 1 PIT0 0 0 0 0
bit w reset
6
0
0
0
0
PITn
Port interrupt trigger n
This field defines the trigger behavior of the associated port interrupt.
104
Micronas
ADVANCE INFORMATION
VCT 38xxA
154:
1E71
7
155:
IRPMUX0
6 PISIP1 5 4
156:
Interrupt Port Multiplex 0
3 2 PISIP0 1 0 w 0 0
157:
1E72
7
158:
IRPMUX1
6 PISIP3 5 4
159:
Interrupt Port Multiplex 1
3 2 PISIP2 1 0
bit w reset
bit
0
0
0
0
0
0
reset
0
0
0
0
0
0
0
0
PISIPn
Port interrupt special input port n
This field defines the special input port connected to the associated port interrupt (see Table on page 126).
Port Px.y 1 1/4 prescaler output Interrupt (low active) Interrupt (low active) Interrupt (low active) 2 3 4 1 2 3 4 1 2 3 4 Independent of trigger mode Falling edge Rising edge Falling and rising edge trigger mode
Fig. 5-13: Interrupt timing (1/4 Prescaler On)
Port Px.y 32 1/32 prescaler output Interrupt (low active) Interrupt (low active) Interrupt (low active) 1 2 15 16 17 18 31 32 Independent of trigger mode Falling edge trigger Rising edge trigger Falling and rising edge trigger mode
Fig. 5-14: Interrupt timing (1/32 Prescaler On)
Micronas
105
VCT 38xxA
5.10.10.Interrupt Timing The interrupt response time is calculated from the interrupt event up to the first interrupt vector on the address bus (see Fig. 5-15 on page 106). After an interrupt event, the Interrupt Controller starts evaluation with the first falling edge of PH2.
ADVANCE INFORMATION
Evaluation needs one clock cycle until the Interrupt Controller pulls the signal NMI Low. After the falling edge of NMI the CPU finishes the actual command. If the falling edge of NMI happens one clock cycle before an opcode fetch, the following command will be finished too. Then PC and status will be saved on stack before the Low byte of the interrupt vector is written to the address bus.
Interrupt Finish actual command and save status. (Save status = 5 clocks).
PH2
Interrupt Request NMI
A0...23
00FFFA
DMA
Vector 1st Byte Vector 2nd Byte Opcode ISR
RDY
Clear Request Interrupts enabled DMAE
Fig. 5-15: Interrupt timing diagram
106
Micronas
ADVANCE INFORMATION
VCT 38xxA
jump to a new subroutine in RAM (e.g. opcode JSR requires 3 consecutive bytes to be patched). The RAM subroutine then may consist of any number of instructions, ending with a return to the next correct instruction in ROM. In such a way it is possible to include also complex software modules. 5.11.1.Features - patching of read data from up to 10 different ROM locations (24 bit physical address) - automatic insertion of 1 CPU wait state for each patched access
5.11.Memory Patch Module The Memory Patch Module allows the user to modify up to ten hard-wired ROM locations by external means. This function is useful if faulty parts of software or data are detected after the ROM code has been cast into mask ROM. Software loads addresses and the corrected code e.g. from external non-volatile memory into respective registers of the module. The module then will replace faulty code upon address match. Single ROM locations are directly replaced. Longer faulty sequences may be repaired by introducing a
ADB[23:0] DB[7:0]
Patch Cell 0
PMEN
Patch Enable Register
Write/Compare Enable PA[7:0]
Patch Address Register
PA[15:8] PA[23:16]
Patch Data Register
Output Enable PATOE
DBP[7:0] PH2
PSEL9...0
1
Patch Cells 1...9
Sequencer
RDY ROMEN
&
ROMACC
RWQ
Fig. 5-16: Block diagram of patch module
5.11.2.General The logic contains ten patch cells (see Fig. 5-16 on page 107), each consisting of a 24-bit compare register (Patch Address register, PARn), a 24-bit address comparator, a Patch Enable register (PERn) bit and an 8-bit Patch Data register (PDR). The current address information for a ROM access is fed to a bank of ten patch cells. In case of a match in one patch cell, and provided that the corresponding Patch Enable register bit is set, a wait cycle for CPU is included by pulling down the RDY input of CPU for one cycle (see Fig. on page 108). In the meantime the module's logic disables the ROM data bus drivers and instead places the data information from the corresponding Patch Data register on the data bus.
5.11.3.Initialization After reset, as bit PER0.PMEN is reset to 0, all patch cell registers are in Write mode and patch operation is disabled. To initialize a patch cell, first set the corresponding PSEL bit in register PER0 or PER1 as a pointer. Then enter the 24bit address to registers PAR2 (High byte), PAR1 (middle byte) and PAR0 (Low byte) and the desired patch code to register PDR. If desired, repeat the above sequence for other patch cells. Only set one PSEL pointer bit in registers PER0 and PER1 at a time.
Micronas
107
VCT 38xxA
5.11.4.Patch Operation To activate a number of properly initialized patch cells for ROM code patching, set all the corresponding PSEL bits in registers PER1, then PER0, setting bit PER0.PMEN to 1. The Memory Patch Module will immediately start comparing the current address to the setting of the enabled patch cells. In case of a match, the ROM data will be replaced by the corresponding patch cell data register setting. To reconfigure the Memory Patch Module, first set PER0.PMEN to 0. The module will immediately terminate patch operation. .
PH2
w
ADVANCE INFORMATION
5.11.5.Patch Registers
160:
1E64
7 PA7 1
161:
PAR0
5 PA5 1 4
162:
Patch Address Register 0
3 PA3 1 2 PA2 1 1 PA1 1 0 PA0 1
bit w reset
6 PA6 1
PA4 1
163:
1E65
7 PA15 1
164:
PAR1
5 PA13 1 4
165:
Patch Address Register 1
3 PA11 1 2 PA10 1 1 PA9 1 0 PA8 1
bit w reset
6 PA14 1
PA12 1
166:
1E66
7 PA23 1
167:
PAR2
5 PA21 1 4
168:
Patch Address Register 2
3 PA19 1 2 PA18 1 1 PA17 1 0 PA16 1
bit
6 PA22 1
PA20 1
ADB[23:0] A1
A2
A2
A3
A3
reset
DB[7:0]
D1
D2
PD1
D3
PD2
169:
1E67
7 PD7 0 6
170:
PDR
5 PD5 0 4 PD4 0
171:
Patch Data Register
3 PD3 0 2 PD2 0 1 PD1 0 0 PD0 0
RD Y
bit w
PD6 0
P TOE A
reset
R EN OM
172:
1E68
7 PSEL6 0
173:
PER0
5 PSEL4 0 4
174:
Patch Enable Register 0
3 PSEL2 0 2 PSEL1 0 1 PSEL0 0 0 PMEN 0
Fig. 5-17: Patch timing
bit w reset
6 PSEL5 0
PSEL3 0
175:
1E69
7 x x
176:
PER1
5 x x 4 x x
177:
Patch Enable Register 1
3 x x 2 PSEL9 0 1 PSEL8 0 0 PSEL7 0
bit w reset
6 x x
PA23 to 0 Patch Address Upon occurrence of this address the patch cell replaces ROM data with data from PDR. PD7 to 0 Patch Data Data to replace false ROM data at certain address. PSEL0 to 9 Select Patch Cell w1: select cell for write or enable for patch w0: disable patch cell Before writing compare address or replace data of a patch cell, only one cell must be selected. In compare mode one or more patch cells can be selected. PMEN w1: w0: Patch Mode Enable enable patch mode of all cells enable write mode of all cells
108
Micronas
ADVANCE INFORMATION
VCT 38xxA
If telegrams longer than 3 bytes (1 address, 2 data bytes) are received, the software must check the filling condition of the Write-FIFO and, if necessary, fill it up (or read out the Read-FIFO). A variety of status flags is available for this purpose: - The `half full' flag I2CRS.WFH is set if the WriteFIFO is filled with three bytes. - The `empty' flag I2CRS.RFE is set if there is no more data available in the Read-FIFO. - The `busy' flag I2CRS.BUSY is activated by writing any byte to any one of the Write registers. It stays active until the I2C bus activities are stopped after the stop condition generation. Moreover, the ACK-bit is recorded separately on the bus lines for the address and the data fields. However, the interface itself can set the address ACK=0. In any case the two ACK flags show the actual bus condition. These flags remain until the next I2C start condition is generated. For example, the software has to work off the following sequence (ACK=1) to read a 16-bit word from an I2C device address 10H (on condition that the bus is not active): - write 021H to I2CWS0 I2CWD0 I2CWP0 I2CRS
5.12.I2C-Bus Master Interface The I2C bus interface is a pure Master system, Multimaster busses are not realizable. The clock and data terminal pins have open-drain outputs. The I2C bus master interface can operate on two terminals. Terminal 1 is connected to the pins SDA/SCL, terminal 2 can be connected either to the pins P36/P37 or to the pins P22/P23. Please refer to chapter 5.18. on page 126 how to set up the corresponding port pins. The I2C bus master interface is not affected by CPU Slow mode. The bit rate is programmable using a clock prescaler. A complete telegram is assembled by the software out of individual sections. Each section contains an 8-bit data. This data is written into one of the six possible Write registers. Depending on the chosen address, a certain part of an I2C bus cycle is generated. By means of corresponding calling sequences it is therefore possible to join even very long telegrams (e.g. long data files for auto increment addressing of I2C slaves). The software interface contains a 5 word deep WriteFIFO for the control data registers, as well, as a 3 word deep Read FIFO for the received data. Thus most of the I2C telegrams can be transmitted to the hardware without the software having to wait for empty space in the FIFO. An interrupt is generated on two conditions: - The Write-FIFO was filled and reaches the `half full' state. - The Write-FIFO is empty and stop condition is completed. All address and data fields appearing on the bus are constantly monitored and written into the Read-FIFO. The software can then check these data in comparison with the scheduled data. If a read instruction is handled, the interface must set the data word FFH, so that the responding slave can insert its data. In this case the Read-FIFO contains the read-in data.
- write 0FFH to - write 0FFH to - read RFE bit from
- read dev. address from I2CRD - read RFE bit from I2CRS
- read 1st data byte from I2CRD - read RFE bit from I2CRS
- read 2nddata byte from I2CRD The value 21H in the first step results from the device address in the 7 MSBs and the R/W-bit (read=1) in the LSB. If the telegrams are longer, the software has to ensure that neither the Write-FIFO nor the Read-FIFO can overflow. - To write data to this device: - write 20H to - write 1st databyte to - write 2nd databyte to I2CWS0 I2CWD0 I2CWP0
The bus activity starts immediately after the first write to the Write-FIFO. The transmission can be synchronized by an artificial extension of the Low phase of the clock line. Transmission is not continued until the state of the clock line is High once again. Thus, an I2C slave device can adjust the transmission rate to its own abilities.
Micronas
109
VCT 38xxA
ADVANCE INFORMATION
WR_Data (subaddress=control info)
D0 to D7 WR
Address Decoder
0
Clock Prescaler half full empty control Write FIFO 5 x 11
1
clk = fOSC
SR2.I2C Terminal 1 SDA/SCL 2
in
SR
out
Write Logic 2 busy Terminal 2 P22/P23 P36/P37
Read Logic Read FIFO 3x8 empty SR D0 to D7 RD_Data Q DAT_ACK SR Q ADR_ACK RD_Status
Start Condition resets ACK flags
Status Register
I2C
Interrupt Source
D0 to D7
Fig. 5-18: Block diagram of I2C bus master interface
110
Micronas
ADVANCE INFORMATION
VCT 38xxA
5.12.1.I2C Bus Master Interface Registers
1T SDA SCL 1/2T 1T 1/4T
178:
1FD0
7
179:
I2CWS0
5 4
180:
I2C Write Start Register 0
3 2 1 0
bit w reset
6
I2C Address 0 0 0 0 0 0 0 0
Writing this register moves I2C start condition, I2C Address and ACK=1 into the Write FIFO.
Fig. 5-19: Start condition I2C bus
181:
1FD1
7
182:
I2CWS1
5 4
183:
I2C Write Start Register 1
3 2 1 0
bit w
6
I2C Address 0 0 0 0 0 0 0 0
1T SDA SCL 1/4T 1/2T 1/4T
reset
Writing this register moves I2C start condition, I2C Address and ACK=0 into the Write FIFO. repeated 8 times
184:
1FD2
7
185:
I2CWD0
5 4
186:
I2C Write Data Register 0
3 2 1 0
bit w reset
6
I2C Data 0 0 0 0 0 0 0 0
Fig. 5-20: Single bit on I2C bus
Writing this register moves I2C Data and ACK=1 into the Write FIFO.
187:
1FD3
7
188:
I2CWD1
5 4
189:
I2C Write Data Register 1
3 2 1 0
bit
6
SDA SCL 1/4T 3/4T
w reset 0 0 0
I2C Data 0 0 0 0 0
Writing this register moves I2C Data and ACK=0 into the Write FIFO.
190:
1FD4
7
191:
I2CWP0
5 4
192:
I2C Write Stop Register 0
3 2 1 0
Fig. 5-21: Stop condition I C bus
2
bit w reset
6
I2C Data 0 0 0 0 0 0 0 0
Writing this register moves I2C Data, ACK=1 and I2C stop condition into the Write FIFO.
193:
1FD5
7
194:
I2CWP1
5 4
195:
I2C Write Stop Register 1
3 2 1 0
bit w reset
6
I2C Data 0 0 0 0 0 0 0 0
Writing this register moves I2C Data, ACK=0 and I2C stop condition into the Write FIFO.
Micronas
111
VCT 38xxA
Table 5-11: I2C Bit Rates
196:
ADVANCE INFORMATION
1FD6
7
197:
I2CRD
5 4
198:
I2C Read Data Register
3 2 1 0
bit r reset
6
SPEED 0 1 2 3
Bit Rate 19.776 Kbit/s 2.531 Mbit/s 1.266 Mbit/s 844 Kbit/s 633 Kbit/s ... 19.931 Kbit/s
I2C Data 0 0 0 0 0 0 0 0
Reading this register returns the content of the Read FIFO.
199:
1FD7
7 x 0
200:
I2CRS
5 AACK 0 4
201:
I2C Read Status Register
3 BUSY 0 2 WFH 0 1 RFE 0 0 x 0
bit r reset
6 OACK 0
4 ... 127
DACK 0
OACK r: AACK r: DACK r: BUSY r1: r0: WFH r1: r0: RFE r1: r0:
"OR"ed Acknowledge AACK || DACK Address Acknowledge Acknowledge state of address field Data Acknowledge Acknowledge state of data field Busy I2C Master Interface is busy I2C Master Interface is not busy Write-FIFO Half Full Write-FIFO is filled with 3 Bytes Write-FIFO is not half full Read-FIFO Empty Read-FIFO is empty Read-FIFO is not empty SIPS w1: w0: Special Input Port Select use port pair P36, P37 for terminal 2 use port pair P22, P23 for terminal 2
202:
1FDB
7 TERM 1 0 6
203:
I2CM
5 4
204:
I2C Mode Register
3 2 1 0
bit w reset
SPEED 0 0 0 0 1 0
TERM w1: w0: SPEED w:
Terminal Select Terminal 1 Terminal 2 Speed Select I2C Bit Rate = fOSC / (4 * SPEED)
205:
1E73
7
206:
I2CPS
5 4
207:
I2C Port Select Register
3 2 1 0 SIPS
bit w reset
6
0
0
0
0
0
0
0
0
112
Micronas
ADVANCE INFORMATION
VCT 38xxA
5.13.1.Features - 16-bit auto reload counter - Time value readable - Interrupt source output - Frequency output
5.13.Timer T0 and T1 Timer T0 and T1 are 16-bit auto reload down counters. They serve to deliver a timing reference signal, to output a frequency signal or to produce time stamps.
TIM x w fOSC/21 fOSC/29 fOSC/2
17
0
Reload-reg. clk 16 16 bit Auto-reload Down counter TIM x zero 1/2
Tx Interrupt Source Tx-OUT
3:1 MUX
1
r 2 SR1.TIMx
TIMxM.CSF
Fig. 5-22: Block diagram of timer T0 and T1
5.13.2.Operation The timer's 16-bit down-counter is clocked by the input clock and counts down to zero. Reaching zero, it generates an output pulse, reloads with the content of the TIMx reload register and restarts its travel. T0 and T1 are not affected by CPU Slow mode. The clock input frequency can be selected from three possible values by programming the timer mode register TIMxM.CSF. After reset, both timers are in standby mode (inactive). Prior to entering active mode, proper SW initialization of the Ports assigned to function as Tx-OUT outputs has to be made. The ports have to be configured Special Out (see Section 5.18. on page 126). To initialize a timer, Reload register TIMx has to set to the desired time value, still in standby mode. For entering active mode, set the corresponding enable bit in the Standby register. The timer will immediately start counting down from the time value present in register TIMx. During active mode, a new time value is loaded by writing to the 16-bit register TIMx, High byte first. Upon writing the Low byte, the reload register is set to the new 16-bit value, the counter is reset, and immediately starts down-counting with the new value. On reaching zero, the counter generates a reload signal, which can be used to trigger an interrupt. The same signal is connected to a divide by two scaler to generate the output signal Tx-OUT with a pulse duty factor of 50 %.
The interrupt source output of this module is routed to the Interrupt Controller logic (see Section 5.10. on page 99). The state of the down-counter is readable by reading the 16-bit register TIMx, Low byte first. Upon reading the Low byte, the High byte is saved to a temporary latch, which is then accessed during the subsequent High byte read. Thus, for time stamp applications, read consistency between Low and High byte is guaranteed. Returning a timer to standby mode by resetting the corresponding Enable bit will halt its counter and will set its output to Low. The register TIMx remains unchanged.
Micronas
113
VCT 38xxA
5.13.3.Timer Registers
ADVANCE INFORMATION
208:
1F4E 1F4C
7
209:
TIM0L TIM1L
5 4
210:
Timer 0 Low Byte Timer 1 Low Byte
3 2 1 0
211:
212:
213:
bit r w reset
6
Read Low Byte of down-counter and latch High Byte. Write Low Byte of reload value and reload down-counter. 1 1 1 1 1 1 1 1
214:
1F4F 1F4D
7
215:
TIM0H TIM1H
5 4
216:
Timer 0 High Byte Timer 1 High Byte
3 2 1 0
217:
218:
219:
bit r w reset
6
Read latched High Byte of down-counter. Write High Byte of reload value. 1 1 1 1 1 1 1 1
TIMx have to be read Low byte first and written High byte first.
220:
1F11 1F13
7
221:
TIM0M TIM1M
5 4
222:
Timer 0 Mode Timer 1 Mode
2 1 CSF 0
223:
224:
225:
bit r/w reset
6
3
0
0
0
0
0
0
0
0
CSF r/w:
Clock Selection Field Source of timer clock (see Table 5-12)
Table 5-12: CSF usage
CSF Clock Divider fOSC/21 fOSC/29 fOSC/2
17
Timer Clock 5.0625 MHz 19.775 KHz 77.248 Hz
Timer Increment 197.53 ns 50.568 s 12.945 ms
Timer Period 12.945 ms 3.3140 s 848.39 s
00 01 1x
114
Micronas
ADVANCE INFORMATION
VCT 38xxA
5.14.1.Features - 16-bit free running counter with read out. - 16-bit capture register. - 16-bit compare register. - Input trigger on rising, falling or both edges. - Output action: toggle, Low or High level. - Three different interrupt sources: overflow, input, compare - Designed for interfacing to asynchronous external events
5.14.Capture Compare Module (CAPCOM) The Capture Compare Module (CAPCOM) is a complex relative timer. It comprises a free running 16-bit Capture Compare Counter (CCC) and 2 Capture Compare Subunits (SU). The CCC provides an interrupt on overflow and the timervalue can be read by software. A SU is able to capture the relative time of an external event input and to generate an output signal when the CCC passes a predefined timer value. Three types of interrupts enable interaction with SW. Special functionality provides an interface to the asynchronous external world.
CCCS.CSF fOSC/20 fOSC/24 fOSC/28 fOSC/212
2
4:1 Mux
0 1
clk
CCC
Timer Value
16
ofl
CCCOFL Interrupt Source
SR0.CCC
2 2
CC0I
1 0
CAP CMP OFL LAC RCR X X X
CC0M
MSK MSK MSK FOL OAM IAM
CC0-IN
00 01 10 11 Input Action Logic
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
& CC0OR Interrupt Source
&
>1
3
2
&
CC0-OUT
Low 00 TOGGLE 0 1 10 11 Output Action Logic
>1
16 reset load
A B
=
16-Bit Capture-Register 16-Bit Compare-Register
r w 16
CC0COMP Interrupt Source
Subunit 0
CC0
Timer Value
16
ofl CC1OR Interrupt Source CC1COMP Interrupt Source
CC1-IN
Subunit 1
CC1-OUT
Fig. 5-23: Block diagram of CAPCOM module
Micronas
115
VCT 38xxA
5.14.2.Initialization After system reset the CCC and all SUs are in standby mode (inactive). In standby mode, the CCC is reset to value 0000h. Capture and compare registers CCx are reset. No information processing will take place, e.g. update of interrupt flags. However, the values of registers CCxI and CCxM are only reset by system reset, not by standby mode. Thus, it is possible to program all mode bits in standby mode and a predetermined start-up out of standby mode is guaranteed. Prior to entering active mode, proper SW configuration of the Ports assigned to function as Input Capture inputs and Output Action outputs has to be made. The Output Action ports have to be configured as Special Out and the Input Capture ports as special in (see Section 5.18. on page 126). Please note, that the compare register CCx is reset in standby mode. It can only be programmed in active mode. 5.14.3.Operation of CCC For entering active mode of the entire CAPCOM module set, the enable bit in the standby register. The CCC will immediately start up-counting with the selected clock frequency and will deliver this 16-bit value to the SUs. The state of the counter is readable by reading the 16bit register CCC, Low byte first. Upon reading the Low byte, the High byte is saved to a temporary latch, which is then accessed during the subsequent High byte read. Thus, for time stamp applications, read consistency between Low and High byte is guaranteed. The CCC is free running and will overflow from time to time. This will cause generation of an overflow interrupt event. The interrupt (CCCOFL) is directly fed to the Interrupt Controller and also to all SUs where further processing takes place.
ADVANCE INFORMATION
5.14.3.1. Operation of Subunit
For a proper setup the SW has to program the following SU control bits in registers CCxI and CCxM: Interrupt Mask (MSK), Force Output Logic (FOL, 0 recommended), Output Action mode (OAM), Input Action mode (IAM), Reset Capture register (RCR, 0 recommended), and Lock After Capture (LAC). Refer to section 5.14.5. for details.
Each SU is able to capture the CCC value at a point of time given by an external input event processed by an Input Action Logic. A SU can also change an output line level via an Output Action Logic at a point of time given by the CCC value. Thus, a SU contains a 16-bit capture register CCx to store the input event CCC value, a 16-bit compare register CCx to program the Output Action CCC value, an 8-bit interrupt register CCxI and an 8-bit mode register CCxM. Two types of interrupts per SU enable interaction with SW. For limitations on operating the CAPCOM module in CPU Slow mode, see section 5.14.3.1.15. on page 117. 5.14.3.1.13. Compare and Output Action To activate a SUs compare logic the respective 16-bit compare register CCx has to be programmed, Low byte first. The compare action will be locked until the High byte write is completed. As soon as CCx setting and CCC value match, the following actions are triggered: - The flag CMP in the CCxI register is set. - The CCxCOMP interrupt source is triggered. - The CCxOR interrupt source is triggered when activated. - The Output Action logic is triggered. Four different reactions are selectable for the Output Action signal: according to field CCxM.OAM (Table 5-17) the equal state will lead to a High or Low level, or toggling or inactivity on this output. Another means to control the Output Action is bit CCxM.FOL. E.g. rise-mode and force will set the output pin to High level, fall-mode and force to Low level. This forcing is static, i.e. it will be permanently active and may override compare events. Thus, it is recommended to set and reset shortly after that, i.e. to pulse the bit with SW. Toggle mode of the Output Action logic and forcing leads to a burst with clockfrequency and is not recommended.
116
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parator equal state (maskable ored and non-maskable direct). All interrupt sources act independently, parallel interrupts are possible. The interrupt flags enable SW to determine the interrupt source and to take the appropriate action. Before returning from the interrupt routine the corresponding interrupt flag should thus be cleared by writing a 1 to the corresponding bit location in register CCxI. The interrupts generated by internal logic (CCC Overflow and Comparator equal) will trigger in a predetermined and known way. But as explained in 5.14.3.1.14. erroneous input signals may cause some difficulties concerning the Input Capture input, as well, as interrupt handling. To overcome possible problems the Input Capture Interrupt flag CCxI.CAP is double buffered. If a second or even more input capture interrupt events occur before the interrupt flag is cleared (i.e. SW was not able to keep track), the flag goes to a third state. Two consecutive writes to this bit in register CCxI are then necessary to clear the flag. This enables SW to detect such a multiple interrupt situation and eventually to discard the capture register value which always relates to the latest input capture event and interrupt. The internal CAPCOM module control logic always runs on the oscillator frequency, regardless of CPU Slow mode. Avoid write accesses to the CCxI register in CPU Slow mode, since the logic would interpret one CPU access as many consecutive accesses. This may yield unexpected results concerning the functionality of the interrupt flags. The following procedure should be followed to handle the capture interrupt flag CAP: 1. SW responds to a CAPCOM interrupt, switching to CPU Fast mode if necessary and determining that the source is a capture interrupt (CAP flag =1). 2. The interrupt service routine is processed. 3. Just before returning to main program, the service routine acknowledges the interrupt by writing a 1 to flag CAP. 4. The service routine reads CAP again. If it is reset, the routine can return to main program as usual. If it is still set an external capture event overrun has happened. Appropriate actions may be taken (i.e. discarding the capture register value etc.). 5. go to 3.
5.14.3.1.14. Capture and Input Action The Input Action logic operates independently of the Output Action logic and is triggered by an external input in a way defined by field CCxM.IAM. Following Table 5-18 it can completely ignore events, trigger on rising or falling edge or on both edges. When triggered, the following actions take place: - Flag CCxI.CAP is set. - The CCxOR interrupt source is triggered when activated. - The 16-bit capture register CCx stores the current CCC value, i.e. the "time" of the external event. Read CCx Low byte first. Further compare action will be locked until the subsequent High byte read is completed. Thus a coherent result is ensured, no matter how much time has elapsed between the two reads. Some applications suffer from fast input bursts and a lot of capture events and interrupts in consequence. If the SW cannot handle such a rate of interrupts, this could evoke stack overflow and system crash. To prevent such fatal situations the Lock After Capture (LAC) mode is implemented. If bit CCxI.LAC is set, only one capture event will pass. After this event has triggered a capture, the Input Action logic will lock until it is unlocked again by writing an arbitrary value to register CCxM. Make sure that this write only restores the desired setting of this register. Programming the Input Action logic while an input transition occurs may result in an unexpected triggering. This may overwrite the capture register, lock the Input Action logic if in LAC mode and generate an interrupt. Make sure that SW is prepared to handle such a situation. For testing purposes, a permanent reset (FFFFh) may be forced on capture register CCx by setting bit CCxI.RCR. Make sure that the reset is only temporary. 5.14.3.1.15. Interrupts Each SU supplies two internal interrupt events: 1. Input Capture event and 2. Comparator equal state. As previously explained, interrupt events will set the corresponding flags in register CCxI. In addition to the above mentioned two, the CCC Overflow interrupt event sets flag CCxI.OFL in each SU. Thus, three interrupt events are available in each SU. The corresponding flags are masked with their mask bits in register CCxM and passed to a logical or. The result (CCxOR) is fed to the Interrupt Controller as a first interrupt source. In addition, the Comparator equal (CCxCOMP) interrupt is directly passed to the Interrupt Controller as second interrupt source. Thus a SU offers four types of interrupts: CCC overflow (maskable ored), input capture event (maskable ored) and com-
5.14.4.Inactivation The CAPCOM module is inactivated and returned to standby mode (power down mode) by setting the Enable bit to 0. Section 5.14.2. applies. CCxI and CCxM are only reset by system reset, not by standby mode.
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5.14.5.CAPCOM Registers
ADVANCE INFORMATION
226:
1F7C
7
227:
CCCL
5
228:
CAPCOM Counter Low Byte
3 2 1 0
bit r reset
6
4
This flag is static. As long as FOL is true neither comparator can trigger nor SW can force, by writing another "one", the Output Action logic. After forcing it is recommended to clear FOL unless Output Action logic should not be locked. OAM r/w: IAM r/w: Output Action Mode Defines behavior of Output Action logic. Input Action Mode Defines behavior of Input Action logic.
Read Low Byte and lock CCC. 0 0 0 0 0 0 0 0
229:
1F7D
7
230:
CCCH
5
231:
CAPCOM Counter High Byte
3 2 1 0
bit r reset
6
4
Read High Byte and unlock CCC. 0 0 0 0 0 0 0 0
Table 5-17: OAM usage
The CAPCOM module counter has to be read Low byte first to avoid inconsistencies.
OAM 00
Output Action Logic Modes Disabled, ignore trigger, output Low level. Toggle output. Output Low level. Output High level.
232:
1F14
7
233:
CCCS
5 4
234:
CAPCOM Clock Select
3 2 1 CSF 0
01 10 11
bit w reset
6
0
0
0
0
0
0
0
0
CSF Clock Selection Field w: Source of CCC clock (see Table 5-16) Table 5-16: CSF usage
Table 5-18: IAM usage
IAM
CSF Clock Divider fOSC/20 fOSC/24 fOSC/28 fOSC/2
12
Input Action Logic Modes Disabled, don't trigger. Trigger on rising edge. Trigger on falling edge. Trigger on rising and falling edge.
Timer Clock 10.125 MHz 632.81 KHz 39.551 KHz 2.4719 KHz
Timer Increment 98.765 ns 1.5802 s 25.284 s 404.54 s
Timer Period 6.4727 ms 103.56 ms 1.6570 s 26.512 s
00 01 10 11
00 01 10 11
235:
1F6C 1F70
7 MSK 0
236:
CC0M CC1M
5 MSK 0 4
237:
CAPCOM 0 Mode Register CAPCOM 1 Mode Register
3 OAM 0 0 0 2 1 IAM 0 0
238:
239:
240:
bit r reset
6 MSK 0
FOL 0
MSK w1: w0:
Mask Flag Enable. Disable.
These mask flags refer to the corresponding event flags in CAPCOM interrupt register. FOL r/w1: r/w0: Force Output Action Logic Force Output Action logic. Release Output Action logic.
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241:
1F6D 1F71
7 CAP 0 6
242:
CC0I CC1I
5 OFL 0
243:
CAPCOM 0 Interrupt Register CAPCOM 1 Interrupt Register
3 RCR 0 2 x 0 1 x 0 0 x 0
244:
245:
246:
bit r/w reset
4 LAC 0
CMP 0
CAP r1: r0: w1: CMP r1: r0: w1: OVL r1: r0: w1: LAC r/w1: r/w0: RCR r/w1: r/w0:
1F6E 1F72
7
Capture Event Event. No Event. Clear flag. Compare Event Event. No Event. Clear flag. Overflow Event Event. No Event. Clear flag. Lock After Capture Enable. Disable. Reset Capture Register Reset capture register to FFFFh. Release capture register.
CC0L CC1L
5
247:
248:
249:
CAPCOM 0 Capture/Compare Low Byte CAPCOM 1 Capture/Compare Low Byte
4 3 2 1 0
250:
251:
252:
bit r w reset
6
Read Low Byte of capture register and lock it. Write Low Byte of compare register and lock it. 1 1 1 1 1 1 1 1
253:
1F6F 1F73
7
254:
CC0H CC1H
5
255:
CAPCOM 0 Capture/Compare High Byte CAPCOM 1 Capture/Compare High Byte
4 3 2 1 0
256:
257:
258:
bit r w reset
6
Read High Byte of capture register and unlock it. Write High Byte of compare register and unlock it. 1 1 1 1 1 1 1 1
259:
1E70
7
260:
CCIMUX
5 CCSIP1
261:
CAPCOM Input Multiplex Register
4 3 2 CCSIP0 1 0
bit w reset
6
0
0
0
0
0
0
0
0
CCSIPn
CAPCOM Special Input Port n
This field defines the special input port connected to the associated SU (see Table on page 126).
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5.15.Pulse Width Modulator Each of the 4 available PWMs is an 8-bit reload downcounter with fixed reload interval. It serves to generate a frequency signal with variable pulse width or, with an external low-pass filter, as a digital to analog converter. 5.15.1.Features - 8-bit resolution - standby mode
ADVANCE INFORMATION
PWMx w
0
Pulse Width Register load 8 clk
x: PWM number 0 to 3 y: Standby Register 0 or 2
fOSC/29 fOSC/21
1 0 1
1
S
Q
0
8 bit down counter SRy.PWMx Fig. 5-1: Block diagram of 8-bit PWM
zero
R
PWMx
5.15.2.General A PWM's 8-bit down-counter is clocked by its input clock and counts down to zero. Reaching zero, it stops and sets the output to Low. A load pulse reloads the counter with the content of the PWM register, restarts it and sets the output to High. The repetition rate is 19.775 KHz, the reload period is 50.57 s. The PWMs are not affected by CPU Slow mode. It is recommended that the CPU should not write the PWM registers during Slow mode. 5.15.3.Initialization Prior to entering active mode, proper SW initialization of the Ports assigned to function as PWMx outputs has to be made. The ports have to be configured Special Out (see Section 5.18. on page 126). 5.15.4.Operation After reset, all PWMs are in standby mode (inactive) and the output signal PWMx is Low. For entering active mode, the enable bit in the corresponding standby register has to be set (see Section 5.5. on page 89). The desired pulse width value is then written into register PWMx. Each PWM will start producing its output signal immediately after the next subsequent load pulse. During active mode, a new pulse width value is set by simply writing to the register PWMx. Upon the next subsequent load pulse the PWM will start producing an output signal with the new pulse width value, starting with a High level.
Returning a PWM to standby mode by resetting its respective enable flag will immediately set its output Low. The state of the down-counters is not readable. 5.15.5.PWM Registers
262:
1F50 1F51 1F52 1F53
7
263:
PWM0 PWM1 PWM2 PWM3
5 4
264:
PWM 0 Register PWM 1 Register PWM 2 Register PWM 3 Register
2 1 0
265:
266:
267:
268:
269:
270:
271:
272:
273:
bit w reset
6
3
Pulse width value 0 0 0 0 0 0 0 0
Table 5-19: Pulse Width Programming
Pulse width value 00h 01h 02h : FEh FFh
1
Pulse duty factor 0% (Output is static Low) 1/256 2/256 : 254/256 100% (Output is static High) 1)
) Pulse duty factor 255/256 is not selectable.
120
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5.16.1.Features - 14bit resolution - standby mode
5.16.Tuning Voltage Pulse Width Modulator The Tuning Voltage Pulse Width Modulator (TVPWM), in combination with an external low pass filter, serves as a digital to analog converter to control voltage synthesis tuning. It can also be operated as a normal 8-bit PWM.
0
fOSC/2
1
clk
1
8 bit PWM Counter 8
load
6 bit Frame Counter 6 Extension Logic 6 TVPWML Register pulse pwm
TVPWM Interrupt Source
SR0.TVPWM
Comparator 8 w TVPWMH Register
1
TVPWM
Fig. 5-2: Block Diagram of 14bit Tuning Voltage PWM
5.16.2.General The TVPWM is based on an 8-bit PWM built by a counter and a programmable comparator (see Fig. 5- 2). The overflow of the counter reloads the comparator with the content of the TVPWMH register and sets the TVPWM output to High. Matching the counter value, the comparator sets the TVPWM output to Low. The counter is continually running, producing PWM cycles with a length of 256 T. Depending on the content of the TVPWML register, the 6-bit pulse extension logic will add additional single clock pulses distributed over a frame of 64 reload cycles (see Fig. 5-3). This gives 14-bit resolution when integrating over a complete frame. The frame rate is 309 Hz, the frame period is 3.24 ms.
An interrupt is generated after completion of a frame of 64 reload cycles. The interrupt source output of this module is routed to the Interrupt Controller logic (see Section 5.10. on page 99). The TVPWM is not affected by CPU Slow mode. It is recommended that the CPU should not write the TVPWM registers during Slow mode.
1T
cycle n 256 T
cycle n+1 256 T
Fig. 5-3: TVPWM Timing
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5.16.3.Initialization Prior to entering active mode, proper SW initialization of the Ports assigned to function as TVPWM output has to be made. The ports have to be configured Special Out (see Section 5.18. on page 126). 5.16.4.Operation After reset, the TVPWM is in standby mode (inactive) and the output signal TVPWM is Low. For entering active mode, the enable bit in the corresponding standby register has to be set (see Section 5.5. on page 89). The desired pulse width value is then written into the registers TVPWML and TVPWMH. The TVPWM will start producing its output signal immediately after the next subsequent load pulse. During active mode, a new pulse width value is set by simply writing to the register TVPWML and TVPWMH. Writing TVPWMH will update the comparator and the extension logic with the new register values. Upon the next subsequent load pulse the TVPWM will start producing an output signal with the new pulse width value, starting with a High level. Returning the TVPWM to standby mode by resetting its respective enable flag will not reset its output signal. The state of the counters and the extension logic is not readable. 5.16.5.TVPWM Registers
274:
ADVANCE INFORMATION
1F4A
7
275:
TVPWML
6 5 4
276:
TV PWM Low Byte
3 2 1 0
bit w reset
Pulse width value Low 0 0 0 0 0 0
277:
1F4B
7
278:
TVPWMH
6 5 4
279:
TV PWM High Byte
3 2 1 0
bit w reset
Pulse width value High 0 0 0 0 0 0 0 0
TVPWM has to be written Low byte first.
122
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5.17.1.Features - A/D converter with 10-bit resolution. - Successive approximation, charge balance type. - Input multiplexer with 15 analog channels. - Sample and hold circuit. - 4/8/16/32 s conversion selectable for optimum throughput/accuracy balance. - Zero standby current, 300 A active current.
5.17.A/D Converter (ADC) This 10-bit analog to digital converter allows the conversion of an analog voltage in the range of 0 to URef into a digital value. A multiplexer connects the ADC to one of 15 analog input ports. A sample-and-hold circuit holds the analog voltage during conversion. The duration of the sampling time is programmable. The A/D conversion is done by a charge balance A/D converter using successive approximation.
SR1.ADC 0
VSUPS GNDS P10-17 P20-26
1
4
15
A MUX S&H D
10
2
AD1 TSAMP
r 7 9 6 8 5 7 4 6 3 5 2 4 1 3 0 2 7 6
AD0 CHANNEL x
5 w r 2 1 1 0 0
x
4
x
3
x
EOC CMPO
CMPO Interrupt Source
Fig. 5-4: Block Diagram of the ADC
5.17.2.Operation After reset, the module is off (zero standby current). The module is enabled by the flag SR1.ADC. The user must ensure that the flag End of Conversion (EOC) in register AD0 is true, before he starts to operate the module. A write access to register AD0 indicating sample time and channel number starts the conversion. The flag EOC signalizes the end of conversion. The 10-bit result is stored in the registers AD1 (8 MSB) and AD0. The conversion rate depends on the software, the oscillator frequency and the programmed sample time. The ADC module is not affected by CPU Slow mode.
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5.17.3.Measurement Errors The result of the conversion mirrors the voltage potential of the sampling capacitance (typically 15 pF) at the end of the sampling time. This capacitance has to be charged by the source through the source impedance within the sampling time period. To avoid measurement errors, system design has to make sure that at the end of the sampling period, the potential error on the sampling capacitance is less than 0.1 LSB. Measurement errors may occur, when the voltage of high-impedance sources has to be measured: - To reduce these errors, the sampling time may be increased by programming the field TSAMP in register AD1. - In cases where high-impedance sources are only rarely sampled, a 100-nF capacitor from the input to GNDS is a sufficient measure to ensure that the potential on the sampling capacitance reaches the full source potential, even with the shortest sampling time. - In some high-impedance applications a charge pumping effect may influence the measurement result when two sources are measured alternatingly. 5.17.4.Comparator In addition to the A/D converter the module contains a comparator. The level at the A/D converter input is compared to VSUPS/2. The state of the comparator output can be read at flag CMPO in register AD0. The interrupt source output of this module is routed to the Interrupt Controller logic. The CMPO interrupt source is gated with an internal clock. This is the reason why interrupts are generated as long as the level at the comparator is lower than the internal reference.
ADVANCE INFORMATION
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ADVANCE INFORMATION
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Table 5-21: ADC input multiplexer CHANNEL 0 1 2 Port Pin none P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26
5.17.5.ADC Registers A write access to register AD0 starts the A/D conversion of the written channel number and sampling duration. The flag EOC signals the end of conversion. The result is stored in register AD1 (bit 9 to 2) and in register AD0 (bit 1 and 0).
280:
1FA8
7 EOC 6
281:
AD0
5 x 4 x
282:
ADC Register 0
2 x 1 AN1 0 AN0
bit r w reset
3 x
3 4 5 6
CMPO
TSAMP 0 0 0 0 0
CHANNEL 0 0 0
283:
1FA9
7 AN9 6
284:
AD1
5 AN7 4 AN6
285:
ADC Register 1
2 AN4 1 AN3 0 AN2
7 8 9
bit r reset
3 AN5
AN8
EOC r1: r0:
End of Conversion End of conversion Busy
10 11 12 13 14 15
EOC is reset by a write access to the register AD0. EOC must be true before starting the first conversion after enabling the module by setting SR1.ADC. CMPO r1: r0: TSAMP Comparator Output Input is lower than reference voltage. Input is higher than reference voltage. Sampling Time
AN 9 to 0
Analog Value Bit 9 to 0
TSAMP adjusts the sample time and the conversion time. The total conversion time is 20 clock cycles longer than the sample time. Sampling starts one clock cycle after completion of the write access to AD0. Table 5-20: Sampling time adjustment TSAMP
0H 1H 2H 3H
The 10 bit analog value is in the range of 0 to 1023. The 8 MSB can be read from register AD1. The two LSB can be read from register AD0. The result is available until a new conversion is started.
tSample
20 TOSC 60 TOSC 140 TOSC 300 TOSC
tConversion
40 TOSC 80 TOSC 160 TOSC 320 TOSC
CHANNEL Channel of Input Multiplexer CHANNEL selects from which port pin the conversion is done. The MSB of CHANNEL is bit 3. No port pin is connected to the ADC if the channel 0 is selected. In this case the input of the A/D converter is connected to ground. After reset, CHANNEL is set to zero.
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5.18.Ports There exist different kinds of ports. The universal ports, P1 to P3, serve as digital I/O and have additional special input and output functions. A subset of the universal ports (P10-P17, P20-P26) serves as input for the analog-to-digital converter. The I2C ports SDA, SCL can alternatively be used as digital I/O ports. The analog audio ports AIN1-3, AOUT1-2 can alternatively be used as digital input ports. The 20.25 MHz system clock output CLK20 can alternatively be used as digital output port.
ADVANCE INFORMATION
Table 5-23: Port pin configuration Port Name P10 P11 P12 P13 P14 ADC Input 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Special Output Timer 0 Timer 1 CC0-OUT CC1-OUT TVPWM PWM 0 PWM 1 PWM 2 PWM 3 CLK20 SDA 2 SCL 2 Timer 0 Timer 1 CC0-OUT CC1-OUT TVPWM PWM 0 PWM 1 PWM 2 PWM 3 CLK20 SDA 2 SCL 2 SDA SCL AOUT1 AOUT2 AIN1 AIN2 AIN3 14 15 13 Special Input Port 1 2 3 4 5 6 7 8 9 10 11 12
5.18.1.Port Assignment Table 5-23 shows the assignment of port pins to Special Input and Output functions. Every Special Output function is connected to 2 port pins in parallel and can be activated via the MOD flag in the corresponding port register. The ADC input multiplexer can be connected to 1 of 15 port pins. The output driver of the selected port pin is then forced to open-drain mode. Additionally it can be disabled using the EN flag in the corresponding port register. Every special input function can be connected to 1 of 15 input ports (see Table 5-22). If port number 0 is selected the special input function is connected to ground. Changing the input port may produce temporary glitch signals. Therefore, the corresponding special input function should be disabled before the input port is changed. Table 5-22: Special input configuration Special Input Number 1 2 3 4 5 6 Special Input Function CC0-IN CC1-IN PINT0 PINT1 PINT2 PINT3 Special Input Port 0-15 0-15
P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 0-15 0-15 0-15 0-15 P41 P42 P43 P44 P45 P46
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5.18.2.1. Features - digital I/O port - special input and output function - analog input function - Schmitt trigger input buffer - tristate output - push-pull or open-drain output - 10-mA output current - output supply either 3.3 V or 5.0 V
5.18.2.Universal Ports P1 to P3 There are 24 universal port pins. The universal ports P1 to P3 are each 8 bits wide. In the 64-pin PSDIP package only 12 universal port pins are available (P10-P17, P20-P23).
ADC In x.y VDD PxD read DBy VSS PxVDD
1
Special In x.y Special Out x.y
Q D
Px.y
0
PxVSS
Q D
PxD write
PxM
Q D
PxE
Q D
x: Port number 1 to 3 y: Port pin number 0 to 7
PxO
Fig. 5-5: Universal port circuit Universal ports can be operated in different modes: Table 5-24: Universal ports operating modes Modes Port Mode Normal Input Special Input Normal Output Special Output Function The SW uses the ports as digital input. The port input is additionally connected to specific hardware modules. The SW uses the ports as latched digital tristate output. The port output is directly driven by specific hardware modules.
After reset, all Universal Ports are in normal mode, tristate condition.
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5.18.2.2. Universal Port Mode
286:
ADVANCE INFORMATION
Each port bit can be individually configured to several port modes. The output driver of each pin has to be enabled by setting the EN flag. Using the OUT flag the output stage can be configured to either open drain or push pull output. The MOD flag selects the source of the output value. Table 5-25: Port mode register settings Mode Normal Input MOD x EN 0 D x Function READ of register PxD returns port pin input levels to data bus. WRITE to register PxD changes level of port pin output drivers. READ of register PxD returns the PxD register setting to the data bus. Special Input Special Output x x x Port pin input level is presented to special hardware.
1F90 1F94 1F98
7 D7 0 6 D6 0
287:
P1D P2D P3D
5 D5 0 4 D4 0
288:
Port 1 Data Register Port 2 Data Register Port 3 Data Register
3 D3 0 2 D2 0 1 D1 0 0 D0 0
289:
290:
291:
292:
293:
294:
bit r/w reset
D0-7 r: w:
Universal Port Data Input/Output Read pin level resp. data latch. Write data to data latch.
To use a port pin as software output, the appropriate driver must be activated by setting the EN flag and the MOD flag must be programmed to Normal mode.
Normal Output
0
1
Data
295:
1F91 1F95 1F99
7 OUT7 0 6
296:
P1O P2O P3O
5 OUT5 0 4 OUT4 0
297:
Port 1 Output Register Port 2 Output Register Port 3 Output Register
3 OUT3 0 2 OUT2 0 1 OUT1 0 0 OUT0 0
298:
299:
300:
301:
302:
303:
bit w reset
OUT6 0
OUT0-7 w1: w0:
Output Flag Output driver is open drain Output driver is push pull
304:
1F92 1F96
305:
P1M P2M P3M
5 MOD5 0 4 MOD4 0
306:
Port 1 Mode Register Port 2 Mode Register Port 3 Mode Register
3 MOD3 0 2 MOD2 0 1 MOD1 0 0 MOD0 0
1
1
x
Special hardware drives port pin. READ of register PxD returns port pin input levels to data bus.
307:
308:
309:
310:
1F9A
7 MOD7 0 6
311:
312:
bit w reset
MOD6 0
The Special Input mode is always active. This allows manipulating the input signal to the special hardware through Normal Output operations by software. As the Special Output mode allows reading the pin levels, the output state of the special hardware may be read by the CPU.
MOD0-7 w1: w0:
Normal/Special Mode Flag Special Output Mode Normal Output Mode
The MOD flag defines from which source the pin is driven if the EN flag is true.
313:
1F93 1F97
314:
P1E P2E P3E
5 EN5 0 4 EN4 0
315:
Port 1 Enable Register Port 2 Enable Register Port 3 Enable Register
3 EN3 0 2 EN2 0 1 EN1 0 0 EN0 0
316:
317:
318:
5.18.3.Universal Port Registers Universal Port Data registers PxD contain input/output data of the corresponding port. The "x" in PxD means the number of the port. Thus PxD stands for P1D to P3D.
319:
1F9B
7 EN7 0 6
320:
321:
bit w reset
EN6 0
EN0-7 w1: w0:
Enable Flag Output driver is enabled Output driver is disabled
128
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5.18.4.1. Features - digital I/O port - I2C input and output function - Schmitt trigger input buffer - open-drain output - connected to standby supply
5.18.4.I2C Ports P40 and P41 The I2C ports SDA and SCL can alternatively be used as digital I/O ports. To activate the I2C function of the port pin the corresponding MOD flag has to be set to special mode. In normal mode the port pin serves as digital I/O. The output stage is open-drain only. After reset, the I2C ports are in special mode.
VDD
P4D read DB0/DB1
VSS VDD
1
1
SDA/SCL In
0
P40 P41
0
SDA/SCL Out
Q D
VSS
Q D
P4D write
P4M
Q D
P4E Fig. 5-6: I2C port circuit .
322:
1F9C
7 6
323:
P4D
5 AIN2D 4
324:
Port 4 Data Register
3 2 1 SCLD SCLD 0 SDAD SDAD 0
325:
1F9E
7 6
326:
P4M
5 AIN2M 1 4
327:
Port 4 Mode Register
3 2 1 SCLM 1 0 SDAM 1
bit r w reset
bit w reset
AIN3D
AIN1D AOUT2D AOUT1D
AIN3M 1
AIN1M AOUT2M AOUT1M 1 0 0
0
0
0
0
0
0
SCLD r: w: SDAD r: w:
SCL Data Input/Output Read pin level resp. data latch. Write data to data latch. SDA Data Input/Output Read pin level resp. data latch. Write data to data latch.
SCLM w1: w0: SDAM w1: w0:
328:
SCL Normal/Special Mode Flag Special I2C Output Mode Normal Output Mode SDA Normal/Special Mode Flag Special I2C Output Mode Normal Output Mode
329:
To use the I2C ports as software output, the appropriate drivers must be activated by setting the SCLEN and SDAEN flag and resetting the SCLM and SDAM flags.
1F9F
7 6
P4E
5 4
330:
Port 4 Enable Register
3 2 1 SCLEN 1 0 SDAEN 1
bit w reset
SCLEN w1: w0: SDAEN w1: w0:
SCL Enable Flag Output driver is enabled Output driver is disabled SDA Enable Flag Output driver is enabled Output driver is disabled
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5.18.5.Audio Ports P42 to P46 The analog audio ports AIN1-3, AOUT1-2 can alternatively be used as digital input ports. To activate the audio function of the port pin, the corresponding MOD flag has to be set to Special mode. In Normal mode the port pin serves as digital input. After reset the audio ports are in Normal mode. 5.18.5.1. Features
ADVANCE INFORMATION
- analog audio input or output - digital input port - Schmitt trigger input buffer - special input function
VDD
P4D read DBy
VSS
1
Special In 4.y Audio
P4.y
0
Q
D
y: Port pin number 2 to 6 Fig. 5-7: Audio port circuit
P4M
AINxD r: AOUTxD r:
AINx Data Input Read pin level resp. data latch. AOUTx Data Input Read pin level resp. data latch.
To use the Audio ports as software input, the corresponding flags must be programmed to Normal Input mode. AINxM w1: w0: AOUTxM w1: w0: AINx Normal/Special Mode Flag Special Audio Input Mode Normal Input Mode AOUTx Normal/Special Mode Flag Special Audio Output Mode Normal Input Mode
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ADVANCE INFORMATION
VCT 38xxA
5.18.6.1. Features - programmable driver strength - tristate mode - digital output port
5.18.6.CLK20 Output Port The CLK20 pin delivers the internal 20.25-MHz clock. The output stage is push-pull with programmable driver strength (C20M.DSTR). The CLK20 pin can alternatively be used as digital output port. It is possible to force the CLK20 output either to High or Low (C20M.FSO) or to switch it into tristate mode (C20M.DOD). After reset, the CLK20 port is enabled.
VDD CLK20 VSS 6 DB C20M Fig. 5-8: CLK20 Port Circuit CLK20
331:
1F9D
7
332:
C20M
5 FSO 4
333:
CLK20 Mode Register
3 DOD 2 1 DSTR 0 0 0 0
bit w reset
6
0
0
0
0
DSTR w000: w111: DOD w1: w0: FSO w10: w11:
Driver Strength Output driver strong Output driver weak Disable Output Driver Output driver is high-impedance Output driver is enabled Force Static Output Output driver is forced to 1 Output driver is forced to 0
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5.19.I/O Register Cross Reference Table 5-26: I/O Register Map Addr. 1E00 1E01 1E02 1E03 1E04 1E05 1E06 1E07 1E08 1E09 1E0A 1E0B 1E0C 1E0D 1E0E 1E0F 1E10 1E11 1E12 1E13 1E14 1E15 1E16 1E17 1E18 1E64 1E65 1E66 1E67 1E68 1E69 Mnemonic MASK1L MASK2L MASK3L MASK4L MASK1H MASK2H MASK3H MASK4H CMP1L CMP2L CMP3L CMP4L CMP1H CMP2H CMP3H CMP4H MAP1L MAP2L MAP3L MAP4L MAP1H MAP2H MAP3H MAP4H DMAIM PAR0 PAR1 PAR2 PDR PER0 PER1 Name Mask 1 Low Byte Mask 2 Low Byte Mask 3 Low Byte Mask 4 Low Byte Mask 1 High Byte Mask 2 High Byte Mask 3 High Byte Mask 4 High Byte Compare 1 Low Byte Compare 2 Low Byte Compare 3 Low Byte Compare 4 Low Byte Compare 1 High Byte Compare 2 High Byte Compare 3 High Byte Compare 4 High Byte Map 1 Low Byte Map 2 Low Byte Map 3 Low Byte Map 4 Low Byte Map 1 High Byte Map 2 High Byte Map 3 High Byte Map 4 High Byte DMA Interface Mode Patch Address Register 0 Patch Address Register 1 Patch Address Register 2 Patch Data Register Patch Enable Register 0 Patch Enable Register 1 Mode w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w Reset FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 00 FF FF FF 00 00 00
ADVANCE INFORMATION
Section DMA Interface (chapter 5.9. on page 96)
Memory Patch Module (chapter 5.11. on page 107)
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ADVANCE INFORMATION
VCT 38xxA
Table 5-26: I/O Register Map Addr. 1F01 1F0F 1F00 1F60 1F07 1F08 1F09 1F0A 1FD0 1FD1 1FD2 1FD3 1FD4 1FD5 1FD6 1FD7 1FDB 1E73 Mnemonic CR BR CSW0 CSW1 RC SR0 SR1 SR2 I2CWS0 I2CWS1 I2CWD0 I2CWD1 I2CWP0 I2CWP1 I2CRD I2CRS I2CM I2CPS Name Control Register Banking Register Clock, Supply & Watchdog Register 0 Clock, Supply & Watchdog Register 1 Reset Control Register Standby Register 0 Standby Register 1 Standby Register 2 I2C Write Start Register 0 I2C Write Start Register 1 I2C Write Data Register 0 I2C Write Data Register 1 I2C Write Stop Register 0 I2C Write Stop Register 1 I2C Read Data Register I2C Read Status Register I2C Mode Register I2C Port Select Register Mode r/w r/w w r/w r/w r/w r/w r/w w w w w w w r r w w Reset Section Control Register (chapter 5.4. on page 87) Memory Banking (chapter 5.8. on page 95) Reset Logic (chapter 5.7. on page 90)
-
01 01 FF 00 00 40 00 00 00 00 00 00 00 00 00 02 00
Standby Registers (chapter 5.5. on page 89)
I2C-Bus Master Interface (chapter 5.12. on page 109)
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Table 5-26: I/O Register Map Addr. 1F20 1F21 1F22 1F23 1F24 1F25 1F26 1F27 1F28 1F29 1F2A 1F2B 1F2C 1E71 1E72 1FA8 1FA9 1F4E 1F4F 1F11 1F4C 1F4D 1F13 1F4A 1F4B 1F50 1F51 1F52 1F53 Mnemonic IRC IRRET IRPRI10 IRPRI32 IRPRI54 IRPRI76 IRPRI98 IRPRIBA IRPRIDC IRPRIFE IRP IRPM0 IRPP IRPMUX0 IRPMUX1 AD0 AD1 TIM0L TIM0H TIM0M TIM1L TIM1H TIM1M TVPWML TVPWMH PWM0 PWM1 PWM2 PWM3 Name Interrupt Control Register Interrupt Return Register Interrupt Priority Register, Input 0 and 1 Interrupt Priority Register, Input 2 and 3 Interrupt Priority Register, Input 4 and 5 Interrupt Priority Register, Input 6 and 7 Interrupt Priority Register, Input 8 and 9 Interrupt Priority Register, Input 10 and 11 Interrupt Priority Register, Input 12 and 13 Interrupt Priority Register, Input 14 and 15 Interrupt Pending Register Interrupt Port Mode Interrupt Port Prescaler Interrupt Port Multiplex 0 Interrupt Port Multiplex 1 ADC Register 0 ADC Register 1 Timer 0 Low Byte Timer 0 High Byte Timer 0 Mode Timer 1 Low Byte Timer 1 High Byte Timer 1 Mode TV PWM Low Byte TV PWM High Byte PWM 0 Register PWM 1 Register PWM 2 Register PWM 3 Register Mode r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r w w w w r/w r r/w r/w w r/w r/w w w w w w w w Reset 0C 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 FF FF 00 FF FF 00 00 00 00 00 00 00
ADVANCE INFORMATION
Section Interrupt Controller (chapter 5.10. on page 99)
A/D Converter (ADC) (chapter 5.17. on page 123) Timer T0 and T1 (chapter 5.13. on page 113)
Pulse Width Modulator (chapter 5.15. on page 120)
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ADVANCE INFORMATION
VCT 38xxA
Table 5-26: I/O Register Map Addr. 1F6C 1F6D 1F6E 1F6F 1F70 1F71 1F72 1F73 1F7C 1F7D 1F14 1E70 1F90 1F91 1F92 1F93 1F94 1F95 1F96 1F97 1F98 1F99 1F9A 1F9B 1F9C 1F9E 1F9F 1F9D 1FFB 1FFC 1FFD 1FFE 1FFF Mnemonic CC0M CC0I CC0L CC0H CC1M CC1I CC1L CC1H CCCL CCCH CCCS CCIMUX P1D P1O P1M P1E P2D P2O P2M P2E P3D P3O P3M P3E P4D P4M P4E C20M TST5 TST4 TST3 TST1 TST2 Name CAPCOM 0 Mode Register CAPCOM 0 Interrupt Register CAPCOM 0 Capture/Compare Low Byte CAPCOM 0 Capture/Compare High Byte CAPCOM 1 Mode Register CAPCOM 1 Interrupt Register CAPCOM 1 Capture/Compare Low Byte CAPCOM 1 Capture/Compare High Byte CAPCOM Counter Low Byte CAPCOM Counter High Byte CAPCOM Clock Select CAPCOM Input Multiplex Register Port 1 Data Register Port 1 Output Register Port 1 Mode Register Port 1 Enable Register Port 2 Data Register Port 2 Output Register Port 2 Mode Register Port 2 Enable Register Port 3 Data Register Port 3 Output Register Port 3 Mode Register Port 3 Enable Register Port 4 Data Register Port 4 Mode Register Port 4 Enable Register CLK20 Mode Register Test Register 5 Test Register 4 Test Register 3 Test Register 1 Test Register 2 Mode r/w r/w r/w r/w r/w r/w r/w r/w r r w w r/w w w w r/w w w w r/w w w w r/w w w w r w w w w Reset 00 00 FF FF 00 00 FF FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 73 03 00 00 00 00 00 00 Test Registers (chapter 5.6. on page 90) Ports (chapter 5.18. on page 126) Section Capture Compare Module (CAPCOM) (chapter 5.14. on page 115)
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6. Specifications 6.1. Outline Dimensions
ADVANCE INFORMATION
SPGS703000-1(P64)/1E
64
33
1
32
57.7 0.1
0.8 0.2 3.8 0.1
19.3 0.1 18 0.05
0.28 0.06 3.2 0.2 1 0.05 1.778 0.48 0.06 31 x 1.778 = 55.1 0.1 20.3 0.5
Fig. 6-1: 64-Pin Plastic Shrink Dual-Inline Package (PSDIP64) Weight approximately 9.0 g Dimensions in mm
0.17 0.06 96 65
31 x 0.8 = 24.8 0.1 0.8
97
64 0.8 0.34 0.05
128
33
1 31.2 0.1
32 3.775 0.325
3.4 0.2 0.1 28 0.1
SPGS706000-5(P128)/1E
Fig. 6-2: 128-Pin Plastic Metric Quad Flat Package (PMQFP128) Weight approximately 5.4 g Dimensions in mm
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31 x 0.8 = 24.8 0.1
31.2 0.1
28 0.1
2.1 0.20 2.540 x 19 = 48.26 0.2 2.540 0.15 0.4 0.1
T R P N M L K J H G 0.8 F E D C B A 0.2 1 0.1 4.80 0.20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 0.1 EXTRA PIN
2.540 0.15
0.46 0.05
0.2
D0029/1E
2.540 x 19 = 48.26 0.2
Fig. 6-3: 257-Pin Ceramic Pin Grid Array (CPGA257) Weight approximately 32 g Dimensions in mm
Micronas
Y W V U
ADVANCE INFORMATION
VCT 38xxA
137
VCT 38xxA
6.2. Pin Connections and Short Descriptions NC = not connected LV = if not used, leave vacant X = obligatory; connect as described in circuit diagram Pin No.
PSDIP 64-pin PMQFP 128-pin CPGA 257-pin
ADVANCE INFORMATION
IN = Input OUT = Output SUPPLY = Supply Pin
Pin Name
Type
Connection
(If not used)
Short Description
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
33 34 37 38 35 36 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 89 76 77 78 90 91 92 93
A-1 C-2 C-1 E-2 B-1 D-2 D-1 F-2 E-1 G-2 F-1 H-2 G-1 H-1 J-1 K-1 L-1 M-1 N-1 N-2 P-1 P-2 Y-16 W-8 Y-7 Y-8 W-16 Y-17 W-17 Y-18
P17 P16 VSUPP1 GNDP1 P15 P14 P13 P12 P11 P10 VOUT VRT SGND GNDAF VSUPAF CBIN CIN1 CIN2/ CRIN VIN1 VIN2 VIN3 VIN4 TEST HOUT VSUPD GNDD FBLIN RIN GIN BIN
IN/OUT IN/OUT SUPPLY SUPPLY IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT OUT IN IN SUPPLY SUPPLY IN IN IN IN IN IN IN IN OUT SUPPLY SUPPLY IN IN IN IN
LV LV X X LV LV LV LV LV LV LV X GNDAF X X VRT VRT VRT VRT VRT VRT VRT GNDS X X X GNDAB GNDAB GNDAB GNDAB
Port 1, Bit 7 Port 1, Bit 6 Supply Voltage, Port 1 Ground, Port 1 Port 1, Bit 5 Port 1, Bit 4 Port 1, Bit 3 Port 1, Bit 2 Port 1, Bit 1 Port 1, Bit 0 Analog Video Output Reference Voltage Top, Video ADC Signal Ground for Analog Input Ground, Analog Front-end Supply Voltage, Analog Front-end Analog Component Cb Input Analog Chroma 1 Input Analog Chroma 2 Input / Analog Component Cr Input Analog Video 1 Input Analog Video 2 Input Analog Video 3 Input Analog Video 4 Input Test Pin, reserved for Test Horizontal Drive Output Supply Voltage, Digital Circuitry Ground, Digital Circuitry Fast Blank Input Analog Red Input Analog Green Input Analog Blue Input
138
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ADVANCE INFORMATION
VCT 38xxA
Pin No.
PSDIP 64-pin PMQFP 128-pin CPGA 257-pin
Pin Name
Type
Connection
(If not used)
Short Description
31 32 33 34
94 95 96 97
W-18 Y-19 W-19 Y-20
VPROT SAFETY HFLB VERTQ / INTLC
IN IN IN OUT
GNDD GNDD HOUT LV
Vertical Protection Input Safety Input Horizontal Flyback Input Differential Vertical Sawtooth Output Interlace Control Output
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 122 123 120 121 117 118 119 62 63 64
V-19 W-20 U-19 V-20 T-19 U-20 R-19 T-20 P-19 R-20 N-19 P-20 N-20 M-20 L-20 K-20 J-20 H-20 H-19 E-19 D-20 F-19 E-20 G-20 G-19 F-20 V-2 W-1 W-2
VERT EW SENSE GNDM RSW1 RSW2 SVMOUT ROUT GOUT BOUT VSUPAB GNDAB VRD XREF AIN3 AIN2 AIN1 AOUT2 AOUT1 VSUPS GNDS XTAL1 XTAL2 RESQ SCL SDA P23 P22 P21
OUT OUT IN SUPPLY OUT OUT OUT OUT OUT OUT SUPPLY SUPPLY IN IN IN IN IN OUT OUT SUPPLY SUPPLY IN OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT
LV LV GNDAB X LV LV VSUPAB VSUPAB VSUPAB VSUPAB X X X X GNDS GNDS GNDS LV LV X X X X X X X LV LV LV
Differential Vertical Sawtooth Output Vertical Parabola Output Sense ADC Input Ground, MADC Input Range Switch1 for Measurement ADC Range Switch2 for Measurement ADC Scan Velocity Modulation Output Analog Red Output Analog Green Output Analog Blue Output Supply Voltage, Analog Back-end Ground, Analog Back-end DAC Reference Reference Input for RGB DACs Analog Audio 3Input Analog Audio 2Input Analog Audio 1 Input Analog Audio 2 Output Analog Audio 1 Output Supply Voltage, Standby Ground, Standby Analog Crystal Input Analog Crystal Output Reset Input/Output, Active Low I2C Bus Clock I2C Bus Data Port 2, Bit 3 Port 2, Bit 2 Port 2, Bit 1
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ADVANCE INFORMATION
Pin No.
PSDIP 64-pin PMQFP 128-pin CPGA 257-pin
Pin Name
Type
Connection
(If not used)
Short Description
64
65 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 55
Y-1 A-20 B-18 A-19 B-17 A-18 B-16 A-17 B-15 A-16 B-14 A-15 B-13 A-14 A-13 A-12 A-11 A-10 A-9 A-8 B-8 A-7 B-7 A-6 B-6 A-5 B-5 A-4 B-4 A-3 B-3 A-2 B-2 R-1
P20 ADB17 VSUPADB GNDADB ADB16 ADB15 ADB14 ADB13 ADB12 ADB11 ADB10 ADB9 ADB8 ADB7 ADB6 ADB5 VSUPADB GNDADB ADB4 ADB3 ADB2 ADB1 ADB0 DB0 DB1 DB2 DB3 VSUPDB GNDDB DB4 DB5 DB6 DB7 DISINTROM
IN/OUT OUT SUPPLY SUPPLY OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT SUPPLY SUPPLY OUT OUT OUT OUT OUT IN/OUT IN/OUT IN/OUT IN/OUT SUPPLY SUPPLY IN/OUT IN/OUT IN/OUT IN/OUT IN
LV LV X X LV LV LV LV LV LV LV LV LV LV LV LV X X LV LV LV LV LV LV LV LV LV X X LV LV LV LV X
Port 2, Bit 0 Address Bus 17 Supply Voltage, Address Bus Ground, Address Bus Address Bus 16 Address Bus 15 Address Bus 14 Address Bus 13 Address Bus 12 Address Bus 11 Address Bus 10 Address Bus 9 Address Bus 8 Address Bus 7 Address Bus 6 Address Bus 5 Supply Voltage, Address Bus Ground, Address Bus Address Bus 4 Address Bus 3 Address Bus 2 Address Bus 1 Address Bus 0 Data Bus 0 Data Bus 1 Data Bus 2 Data Bus 3 Supply Voltage, Data Bus Ground, Data Bus Data Bus 4 Data Bus 5 Data Bus 6 Data Bus 7 Disable Internal ROM
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ADVANCE INFORMATION
VCT 38xxA
Pin No.
PSDIP 64-pin PMQFP 128-pin CPGA 257-pin
Pin Name
Type
Connection
(If not used)
Short Description
56 57 58 59 60 61 66 67 68 69 70 71 72 73 74 75 79 80 81 82 83 84 85 86 87 88 124 125 126 127 128
R-2 T-1 T-2 U-1 U-2 V-1 W-3 Y-2 W-4 Y-3 W-5 Y-4 W-6 Y-5 W-7 Y-6 Y-9 Y-10 Y-11 Y-12 Y-13 W-13 Y-14 W-14 Y-15 W-15 D-19 C-20 C-19 B-20 B-19
P27 P26 P25 P24 VSUPP2 GNDP2 VBCLK VB7 VB6 VB5 VB4 VB3 VB2 VB1 VB0 CLK20 P37 P36 P35 P34 VSUPP3 GNDP3 P33 P32 P31 P30 WE1Q WE2Q OE1Q OE2Q ADB18
IN/OUT IN/OUT IN/OUT IN/OUT SUPPLY SUPPLY IN IN IN IN IN IN IN IN IN OUT IN/OUT IN/OUT IN/OUT IN/OUT SUPPLY SUPPLY IN/OUT IN/OUT IN/OUT IN/OUT OUT OUT OUT OUT OUT
LV LV LV LV X X GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD LV LV LV LV LV X X LV LV LV LV LV LV LV LV LV
Port 2, Bit 7 Port 2, Bit 6 Port 2, Bit 5 Port 2, Bit 4 Supply Voltage, Port 2 Ground, Port 2 Video Bus Clock Video Bus 7 Video Bus 6 Video Bus 5 Video Bus 4 / Bond 0=16k Text RAM Video Bus 3 / Bond 1=CTI Video Bus 2 / Bond 2=Scaler Video Bus 1 / Bond 3=Comb Filter Video Bus 0 / Bond 4=VDP Full/Lite 20 MHz System Clock Output Port 3, Bit 7 Port 3, Bit 6 Port 3, Bit 5 Port 3, Bit 4 Supply Voltage, Port 3 Ground, Port 3 Port 3, Bit 3 Port 3, Bit 2 Port 3, Bit 1 Port 3, Bit 0 Write Enable Output 1 Write Enable Output 2 Output Enable Output 1 Output Enable Output 2 Address Bus 18
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6.3. Pin Descriptions for PSDIP64 package Pin 1,2,5-10, P10-P17 - I/O Port (Fig. 6-28) These pins provide CPU controlled I/O ports. Pin 3, VSUPP1* - Supply Voltage, Port 1 Driver This pin is used as supply for the I/O port 1 driver. Pin 4, GNDP1* - Ground, Port 1 Driver This is the ground reference for the I/O port 1 driver. Pin 11, VOUT- Analog Video Output (Fig. 6-13) The analog video signal that is selected for the main (luma, CVBS) adc is output at this pin. An emitter follower is required at this pin. Pin 12, VRT - Reference Voltage Top (Fig. 6-14) Via this pin, the reference voltage for the A/D converters is decoupled. The pin is connected with 10 F/47 nF to the Signal Ground Pin. Pin 13, SGND - Signal GND for Analog Input This is the high quality ground reference for the video input signals. Pin 14, GNDAF* - Ground, Analog Front-end This pin has to be connected to the analog ground. No supply current for the digital stages should flow through this line. Pin 15, VSUPAF* - Supply Voltage, Analog Front-end This pin has to be connected to the analog supply voltage. No supply current for the digital stages should flow through this line. Pin 16,18, CBIN,CRIN - Analog Chroma Component Input (Fig. 6-11) These pins are used as the chroma component (CB, CR) inputs required for the analog YUV Interface. The input signal must be AC-coupled. The CRIN pin can alternatively be used as the second SVHS chroma input (CIN2). Pin 17,18, CIN1,CIN2 - Analog Chroma Input (Fig. 6- 11) These are the analog chroma inputs. A S-VHS chroma signal is converted using the chroma (Video 2) AD converter. A resistive divider is used to bias the input signal to the middle of the converter input range. The input signal must be AC-coupled. The CIN2 pin can alternatively be used as the chroma component (CR) input required for the analog YUV Interface. Pins 19-22, VIN1-4 - Analog Video Input (Fig. 6-10) These are the analog video inputs. A CVBS or S-VHS luma signal is converted using the luma (Video 1) AD converter. The input signal must be AC-coupled. Pin 23, TEST - Test Input (Fig. 6-6) This pin enables factory test modes. For normal operation, it must be connected to ground.
ADVANCE INFORMATION
Pin 24, HOUT - Horizontal Drive Output (Fig. 6-17) This open drain output supplies the drive pulse for the horizontal output stage. The polarity and gating with the flyback pulse are selectable by software. Pin 25, VSUPD* - Supply Voltage, Digital Circuitry Pin 26, GNDD* - Ground, Digital Circuitry This is the ground reference for the digital circuitry. Pin 27, FBLIN - Fast Blank Input (Fig. 6-19) These pins are used to switch the RGB outputs to the external analog RGB inputs. The active level (low or high) can be selected by software. Pin 28,29,30, RIN, GIN, BIN - Analog RGB Input (Fig. 6-15) These pins are used to insert an external analog RGB signal, e.g. from a SCART connector which can by switched to the analog RGB outputs with the fast blank signal. The analog back-end provides separate brightness and contrast settings for the external analog RGB signals. Pin 31, VPROT - Vertical Protection Input (Fig. 6-18) The vertical protection circuitry prevents the picture tube from burn-in in the event of a malfunction of the vertical deflection stage. During vertical blanking, a signal level of 2.5V is sensed. If a negative edge cannot be detected, the RGB output signals are blanked. Pin 32, SAFETY - Safety Input (Fig. 6-18) This is a three-level input. Low level means normal function. At the medium level RGB output signals are blanked. At high level RGB output signals are blanked and horizontal drive is shut off. Pin 33, HFLB - Horizontal Flyback Input (Fig. 6-18) Via this pin the horizontal flyback pulse is supplied to the VCT 38xxA. Pin 34, VERTQ, INTLC - Inverted Vertical Sawtooth Output (Fig. 6-21) / Interlace Output (Fig. 6-20) This pin supplies the inverted signal of VERT. Together with the VERT pin it can be used to drive symmetrical deflection amplifiers. The drive signal is generated with 15-bit precision. The analog voltage is generated by a 4 bit current-DAC with external resistor and uses digital noise shaping. Alternatively this pin supplies the interlace information, the polarity is programmable. Pin 35, VERT - Vertical Sawtooth Output (Fig. 6-21) This pin supplies the drive signal for the vertical output stage. The drive signal is generated with 15-bit precision. The analog voltage is generated by a 4 bit current-DAC with external resistor and uses digital noise shaping.
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ADVANCE INFORMATION
VCT 38xxA
Pin 49, 50, 51, AIN1-3 - Analog Audio Input (Fig. 6- 26) The analog input signal from TUNER or SCART is fed to this pin. The input signal must be AC-coupled. Alternatively these pins can be used as digital I/O ports (Fig. 6-29). Pin 52,53, AOUT1, AOUT2 - Analog Audio Output (Fig. 6-27) These pins are the analog audio outputs. Connections to these pins must use a 680 ohm series resistor as closely as possible to these pins. The output signals are intended to be AC coupled. Alternatively these pins can be used as digital I/O ports (Fig. 6-29). Pin 54, VSUPS* - Supply Voltage, Standby Pin 55, GNDS* - Ground, Standby This is the ground reference for the standby circuitry. Pins 56 and 57, XTAL1 Crystal Input and XTAL2 Crystal Output (Fig. 6-8) These pins are connected to an 20.25 MHz crystal oscillator which is digitally tuned by integrated shunt capacitances. The CLK20 clock signal is derived from this oscillator. Pin 58, RESQ - Reset Input/Output (Fig. 6-7) A low level on this pin resets the VCT 38xxA. The internal CPU can pull down this pin to reset external devices connected to this pin. Pin 59, SCL - I2C Bus Clock (Fig. 6-7) This pin connects to the I2C bus clock line. The signal can be pulled down by external slave ICs to slow down data transfer. Pin 60, SDA - I2C Bus Data (Fig. 6-7) This pin connects to the I2C bus data line. Pin 61-64, P20-P23 - I/O Port (Fig. 6-28) These pins provide CPU controlled I/O ports.
Pin 36, EW - East-West Parabola Output (Fig. 6-22) This pin supplies the parabola signal for the East-West correction. The drive signal is generated with 15 bit precision. The analog voltage is generated by a 4 bit current-DAC with external resistor and uses digital noise shaping. Pin 37, SENSE - Measurement ADC Input (Fig. 6-24) This is the input of the analog to digital converter for the picture and tube measurement. Three measurement ranges are selectable with RSW1 and RSW2. Pin 38, GNDM - Measurement ADC Reference Input This is the ground reference for the measurement A/D converter. Connect this pin to GNDAB Pin 39, 40, RSW1, RSW2 - Range Switch for Measuring ADC (Fig. 6-23) These pins are open drain pulldown outputs. RSW1 is switched off during cutoff and whitedrive measurement. RSW2 is switched off during cutoff measurement only. Pin 41, SVMOUT - Scan Velocity Modulation Output (Fig. 6-16) This output delivers the analog SVM signal. The D/A converter is a current sink like the RGB D/A converters. At zero signal the output current is 50% of the maximum output current. Pin 42, 43, 44, ROUT, GOUT, BOUT - Analog RGB Output (Fig. 6-16) These pins are the analog Red/Green/Blue outputs of the back-end. The outputs are current sinks. Pin 45, VSUPAB* - Supply Voltage, Analog Back-end This pin has to be connected to the analog supply voltage. No supply current for the digital stages should flow through this line. Pin 46, GNDAB* - Ground, Analog Back-end This pin has to be connected to the analog ground. No supply current for the digital stages should flow through this line. Pin 47, VRD - DAC Reference Decoupling (Fig. 6-25) Via this pin the DAC reference voltage is decoupled by an external capacitor. The DAC output currents depend on this voltage, therefore a pulldown transistor can be used to shut off all beam currents. A decoupling capacitor of 4.7 F in parallel to 100 nF (low inductance) is required. Pin 48, XREF - DAC Current Reference (Fig. 6-25) External reference resistor for DAC output currents, typical 10 k to adjust the output current of the D/A converters. (see recommended operating conditions). This resistor has to be connected to analog ground as closely as possible to the pin.
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VCT 38xxA
6.4. Pin Descriptions for PMQFP128 package Pins 1, 4-15, 18-22, 128, ADB0-ADB18 - Address Bus Output (Fig. 6-30) These 19 lines provide the CCU address bus output to access external memory. Pin 2, 16, VSUPADB* - Supply Voltage, Address Bus Driver This pin is used as supply for the address bus driver. Pin 3, 17, GNDADB* - Ground, Address Bus Driver This is the ground reference for the address bus driver. Pins 23-26, 29-32, DB0-DB7 - Data Bus Input/Output (Fig. 6-31) These 8 lines provide the bidirectional CCU data bus to access external memory. Pin 27, VSUPDB* - Supply Voltage, Data Bus Driver This pin is used as supply for the CCU data bus driver. Pin 28, GNDDB* - Ground, Data Bus Driver This is the ground reference for the CCU data bus driver. Pin 55, DISINTROM - Disable Internal ROM Input (Fig. 6-6) A high level at this pin disables the internal CCU program memory during reset. In this case the CCU loads the control word from external address location h'FFF9. Pin 56-59, P27-P24 - I/O Port (Fig. 6-28) These pins provide CCU controlled I/O ports. Pin 60, VSUPP2* - Supply Voltage, Port 2 Driver This pin is used as supply for the I/O port 2 driver. Pin 61, GNDP2* - Ground, Port 2 Driver This is the ground reference for the I/O port 2 driver. Pins 66-74, VBCLK, VB0-VB7 - Digital Video Bus Input (Fig. 6-32) In future versions of VCT 38xxA these pins will provide the ITU-R 656 video interface. As long as the ITU-R 656 video interface is not available, these pins have to be connected to GNDD. Pin 75, CLK20 - Main Clock Output (Fig. 6-9) This is the 20.25 MHz main clock output. Pin 79-82, 85-88, P37-P30 - I/O Port (Fig. 6-28) These pins provide CCU controlled I/O ports. Pin 83, VSUPP3* - Supply Voltage, Port 3Driver This pin is used as supply for the I/O port 3 driver. Pin 84, GNDP3* - Ground, Port 3Driver This is the ground reference for the I/O port 3 driver.
ADVANCE INFORMATION
Pin 124, WE1Q - Write Enable Output 1 (Fig. 6-30) This pin controls the direction of data exchange between the CCU and the external program memory device. Pin 125, WE2Q - Write Enable Output 2 (Fig. 6-30) This pin controls the direction of data exchange between the CCU and external the teletext page memory device. Pin 126, OE1Q - Output Enable Output 1 (Fig. 6-30) This pin is used to enable the output driver of the external program memory device for read access. Pin 127, OE2Q - Output Enable Output 1 (Fig. 6-30) This pin is used to enable the output driver of the external teletext page memory device for read access.
* Application Note: All ground pins should be connected to one low-resistive ground plane. All supply pins should be connected separately with short and low-resistive lines to the power supply. Decoupling capacitors from VSUPxx to GNDxx are recommended as closely as possible to these pins. Decoupling of VSUPD and GNDD is most important. We recommend using more than one capacitor. By choosing different values, the frequency range of active decoupling can be extended.
144
Micronas
ADVANCE INFORMATION
VCT 38xxA
6.5. Pin Configuration
P17 P16 VSUPP1 GNDP1 P15 P14 P13 P12 P11 P10 VOUT VRT SGND GNDAF VSUPAF CBIN CIN1 CIN2/CRIN VIN1 VIN2 VIN3 VIN4 TEST HOUT VSUPD GNDD FBLIN RIN GIN BIN VPROT SAFETY
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51
P20 P21 P22 P23 SDA SCL RESQ XTAL2 XTAL1 GNDS VSUPS AOUT1 AOUT2 AIN1 AIN2 AIN3 XREF VRD GNDAB VSUPAB BOUT GOUT ROUT SVMOUT RSW2 RSW1 GNDM SENSE EW VERT VERTQ HFLB
VCT 38xx
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
Fig. 6-4: 64-pin PSDIP package
Micronas
145
VCT 38xxA
ADVANCE INFORMATION
P35 P34 VSUPP3 GNDP3 P33 P32 P31 P30 TEST FBLIN RIN GIN BIN VPROT SAFETY HFLB
P36 P37 GNDD VSUPD HOUT CLK20 VB0 VB1 VB2 VB3 VB4 VB5 VB6 VB7 VBCLK P20
VERTQ VERT EW SENSE GNDM RSW1 RSW2 SVMOUT ROUT GOUT BOUT VSUPAB GNDAB VRD XREF AIN3 AIN2 AIN1 AOUT2 AOUT1 RESQ SCL SDA XTAL1 XTAL2 VSUPS GNDS WE1Q WE2Q OE1Q OE2Q ADB18
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 97 64 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 1 2 3 4 5 6 7 8 9 63 62 61 60 59 58 57 56 55 54 53 52 51 50
P21 P22 P23 GNDP2 VSUPP2 P24 P25 P26 P27 DISINTROM VIN4 VIN3 VIN2 VIN1 CIN2/CRIN CIN1 CBIN VSUPAF GNDAF SGND VRT VOUT P10 P11 P12 P13 GNDP1 VSUPP1 P14 P15 P16 P17
VCT 38xx
49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
33 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
ADB17 VSUPADB GNDADB ADB16 ADB15 ADB14 ADB13 ADB12 ADB11 ADB10 ADB9 ADB8 ADB7 ADB6 ADB5 VSUPADB
DB7 DB6 DB5 DB4 GNDDB VSUPDB DB3 DB2 DB1 DB0 ADB0 ADB1 ADB2 ADB3 ADB4 GNDADB
146
Micronas
ADVANCE INFORMATION
VCT 38xxA
Fig. 6-5: 128-pin PMQFP package VSUPAF 6.6. Pin Circuits To ADC VSUPS GNDAF GNDS Fig. 6-6: Input pins TEST, DISINTROM VSUPAF VSUPS To ADC GNDAF GNDS Fig. 6-7: Input/Output pins RESQ, SDA, SCL VSUPAF VSUPS P XTAL2
0.5M
Fig. 6-10: Input pins VIN1-VIN4
N
Fig. 6-11: Input pins CIN1, CIN2
To ADC GNDAF Fig. 6-12: Input pins CRIN, CBIN
P
P fXTAL N
XTAL1
N N GNDS
VINx VSUPAF
- +
P
Fig. 6-8: Input/Output pins XTAL1, XTAL2
VREF N GNDAF
VSUPD P N GNDD Fig. 6-9: Output pin CLK20 =V REF - + VSUPAF P VRT ADC Reference SGND Fig. 6-14: Supply pins VRT, SGND Fig. 6-13: Output pin VOUT
Micronas
147
VCT 38xxA
ADVANCE INFORMATION
VSUPAB P P
Clamping
VSUPAB
P
N GNDAB
N GNDAB
Fig. 6-20: Output pin INTLC
Fig. 6-15: Input pins RIN, GIN, BIN VSUPAB P N
Bias
Flyback
P GNDAB
P
VERTQ VERT N GNDAB
N
Fig. 6-16: Output pins ROUT, GOUT, BOUT, SVMOUT
Fig. 6-21: Output pins VERT, VERTQ N GNDD Fig. 6-17: Output pin HOUT P VSUPAB VREF GNDAB Fig. 6-18: Input pins SAFETY, VPROT, HFLB Fig. 6-22: Output pin EW P VSUPAB
VEWXR
N GNDAB
N VSUPAB VREF GNDAB Fig. 6-19: Input pin FBLIN GNDAB Fig. 6-23: Output pins RSW1, RSW2
148
Micronas
ADVANCE INFORMATION
VCT 38xxA
VSUPS P N N N P P
VSUPAB
Fig. 6-24: Input pin SENSE
GND AB Fig. 6-29: Input pins P42-P46 VSUPAB
VRD int. ref. voltage
+ -
ref. current P XREF GNDAB N
VSUPADB
Fig. 6-25: Supply pins XREF, VRD GNDADB Fig. 6-30: Output pins ADB0-ADB18, OE1, OE2, WE1, WE2
40 k
2.5 V
GNDAB Fig. 6-26: Input pins AIN1-3
VSUPS P
VSUPDB
N
80 k
GNDDB Fig. 6-31: Input/Output pins DB0-DB7
2.5 V
GNDAB Fig. 6-27: Output pins AOUT1, AOUT2
VSUPD
GNDD VSUPS P VSUPPx Fig. 6-32: Input pins VB0-VB7, VBCLK
to ADC
N GND Px
Fig. 6-28: Input/Output pins P10-P17, P20-P27, P30P37
Micronas
149
VCT 38xxA
6.7. Electrical Characteristics 6.7.1. Absolute Maximum Ratings
Symbol TA TC TC TS PTOT VSUPx VI VO VIO Parameter Ambient Operating Temperature Case Temperature (PSDIP64) Case Temperature (PMQFP128) Storage Temperature Total Power Dissipation Supply Voltage Input Voltage, all Inputs Output Voltage, all Outputs Input/Output Voltage, all Open Drain Outputs VSUPx Pin Name Min.
ADVANCE INFORMATION
Max. 65 115 115 125 1400 6 VSUPx+0.31) VSUPx+0.3 6
1)
Unit
- - - -40 - -0.3 -0.3 -0.3 -0.3
C C C
C mW V V V V
1)
Refer to Pin Circuits (chapter 6.6. on page 147)
Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions/Characteristics" of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
6.7.2. Recommended Operating Conditions 6.7.2.1. General Recommendations
Symbol TA fXTAL VSUPA VSUPD Parameter Ambient Operating Temperature Clock Frequency Analog Supply Voltage XTAL1/2 VSUPAF VSUPAB VSUPS VSUPD VSUPVDP VSUPTPU VSUPCCU VSUPPx VSUPDB VSUPADB VSUPAF VSUPAB VSUPD VSUPS VSUPVDP VSUPTPU VSUPCCU Pin Name Min. 0 Typ. Max. 65 Unit C MHz V
-
20.25 5.0
-
4.75
-
5.25
Digital Supply Voltage
3.15
3.3
3.45
V
VSUPP
Port Supply Voltage
3.15
3.3/5.0
5.25
V
VSUPOFF
Standby Supply Voltage
0
-
0.5
V
VSUP
Difference between Standby and Emulator Supply Voltage
0
-
0.3
V
150
Micronas
ADVANCE INFORMATION
VCT 38xxA
6.7.2.2. Analog Input and Output Recommendations
Symbol Audio CAIN VAIN RLAOUT CLAOUT RSAOUT Video VVIN VCIN CVIN CCIN CCCIN RGB Rxref CRGBIN
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Input Coupling Capacitor Audio Inputs Audio Input Level Audio Output Load Resistance Audio Output Load Capacitance Audio Output Serial Resistance
AIN1-3
- -
330
-
nF
- - -
680
1.0
VRMS k nF
AOUT1-2
10
-
1.0
- -
-
Video Input Level
VIN1-4, CIN1-2 CRIN, CBIN VIN1-4
0.5
1.0
3.5
V
Chroma Input Level Input Coupling Capacitor Video Inputs Input Coupling Capacitor Chroma Inputs Input Coupling Capacitor Component Inputs
- - - -
700 680
- - - -
mV nF
CIN1-2
1
nF
CRIN, CBIN
220
nF
RGB-DAC Current defining Resistor RGB Input Coupling Capacitor
XREF RIN GIN BIN
9.5
10 15
10.5
k nF
-
-
Deflection Rload Cload Deflection Load Resistance Deflection Load Capacitance EW, VERT, VERTQ
- -
6.8 68
- -
k nF
Micronas
151
VCT 38xxA
6.7.2.3. Recommended Crystal Characteristics
Symbol TA fP Parameter Operating Ambient Temperature Parallel Resonance Frequency with Load Capacitance CL = 13 pF Accuracy of Adjustment Frequency Temperature Drift Series Resistance Shunt Capacitance Motional Capacitance Min. 0 - Typ. - 20.250000
ADVANCE INFORMATION
Max. 65 -
Unit
C
MHz
fP/fP fP/fP
RR C0 C1
- - - 3 20
- - - - -
20 30
25 7 30
ppm ppm
pF fF
Load Capacitance Recommendation CLext External Load Capacitance 1) from pins to Ground (pin names: Xtal1 Xtal2) - 3.3 - pF
DCO Characteristics 2,3) CICLoadmin Effective Load Capacitance @ min. DCO- Position, Code 0, package: 64PSDIP Effective Load Capacitance Range, DCO Codes from 0..255 3 4.3 5.5 pF
CICLoadrng
1)
11
12.7
15
pF
Remarks on defining the External Load Capacitance:
External capacitors at each crystal pin to ground are required. They are necessary to tune the effective load capacitance of the PCBs to the required load capacitance CL of the crystal. The higher the capacitors, the lower the clock frequency results. The nominal free running frequency should match fp MHz. Due to different layouts of customer PCBs the matching capacitor size should be determined in the application. The suggested value is a figure based on experience with various PCB layouts. Tuning condition: Code DVCO Register=-720
2)
Remarks on Pulling Range of DCO:
The pulling range of the DCO is a function of the used crystal and effective load capacitance of the IC (CICLoad +CLoadBoard). The resulting frequency fL with an effective load capacitance of CLeff = CICLoad + CLoadBoard is: 1 + 0.5 * [ C1 / (C0 + CLeff) ] fL = fP * _______________________ 1 + 0.5 * [ C1 / (C0 + CL) ]
3)
Remarks on DCO codes
The DCO hardware register has 8 bits, the fp control register uses a range of -2048...2047
152
Micronas
ADVANCE INFORMATION
VCT 38xxA
6.7.3. Characteristics If not otherwise designated under test conditions, all characteristics are specified for recommended operating conditions (see Section 6.7.2. on page 150).
6.7.3.1. General Characteristics
Symbol PTOT PSTDBY IVSUPS IVSUPS IVSUPD IVSUPP IVSUPAF IVSUPAB IL
Parameter Total Power Dissipation Standby Power Dissipation Current Consumption Standby Mode Current Consumption Standby Supply Current Consumption Digital Circuitry Current Consumption Port Circuitry Current Consumption Analog Front-end Current Consumption Analog Back-end Input and Output Leakage Current
Pin Name
Min.
Typ. 850 tbd tbd
Max. 1350 tbd tbd
Unit mW mW mA
Test Conditions
-
VSUPS
- - - - - - - -
VSUPD = VSUPP = VSUPAF = VSUPAB = VSUPDB = VSUPADB = 0V SR0 = SR1 = SR2 = 0 normal operation
15
23
mA
VSUPD VSUPP VSUPAF VSUPAB All I/O Pins
55
83
mA
-
-
mA
depends on port load
48
72
mA
50
100
mA
depends on contrast and brightness settings
-
1
A
6.7.3.2. Test Input
Symbol VIL VIH
Parameter Input Low Voltage Input High Voltage
Pin Name TEST
Min.
Typ.
Max. 0.8
Unit V V
Test Conditions
-
2.0
- -
-
Micronas
153
VCT 38xxA
6.7.3.3. Reset Input
ADVANCE INFORMATION
Symbol VBG tBG
Parameter Internal Reference Voltage Internal Voltage Reference Setup Time after Power-Up RESET Comparator Reference Voltage RESET Comparator Hysteresis, symmetrical to VREFR ALARM Comparator Reference Voltage ALARM Comparator Hysteresis, symmetrical to VREFA RESET, ALARM Comparator Delay Time Power On Reset Comparator Reference Voltage
Pin Name RESQ
Min. 1.125
Typ. 1.25 30
Max. 1.375 60
Unit V us
Test Conditions
- -
VREFR
1*VBG
-
V
RVlh- RVhl VREFA
0.25
0.313
0.375
V
-
2*VBG
-
V
AVlh- AVhl tCDEL
0.1
0.135
0.15
V
- -
-
100
ns
Overdrive=50mV
VREFPOR
VSUPS
2*VBG
-
V
6.7.3.4. I2C Bus Interface
Symbol VIL VIH VOL VIH tF tR fSCL tLOW tHIGH tSU Data tHD Data
Parameter Input Low Voltage
Pin Name SDA, SCL
Min. -
Typ. -
Max. 0.3* VSUPS -
Unit V
Test Conditions
Input High Voltage
0.6* VSUPS -
-
V
Output Low Voltage
-
0.4 0.6 5 300 300 400 - - - 0.9
V V pF ns ns kHz
Il = 3 mA Il = 6 mA
Input Capacitance Signal Fall Time Signal Rise Time Clock Frequency Low Period of SCL High Period of SCL Data Set Up Time to SCL high DATA Hold Time to SCL low SDA SCL
- - - 0 1.3 0.6 100 0
- - - - - - - -
CL = 400 pF CL = 400 pF
s s
ns
s
154
Micronas
ADVANCE INFORMATION
VCT 38xxA
6.7.3.5. 20-MHz Clock Output
Symbol VOL VOH
Parameter Output Low Voltage
Pin Name CLK20
Min.
Typ.
Max. 0.4
Unit V
Test Conditions IOL = tbd, strength tbd
-
- -
Output High Voltage
VSUPD - 0.4
VSUPD
V
-IOL = tbd, strength tbd
6.7.3.6. Analog Video Output
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
VOUT AGCVOUT DNLAGC VOUTDC BW
Output Voltage AGC Step Width, VOUT AGC Differential Non-Linearity DC-Level VOUT Bandwidth
VOUT
1.7
2.0 1.333
2.3
VPP dB
VVIN = 1 VPP, AGC = 0 dB 3 Bit Resolution = 7 Steps 3 MSB's of main AGC clamped to back porch Input: -2 dBr of main ADC range, CL 10 pF Input: -2 dBr of main ADC range, CL 10 pF 1 MHz, 5 Harmonics
0.5 1 6 10 -
LSB V MHz
THD
VOUT Total Harmonic Distortion
-45
-40
dB
CLVOUT ILVOUT
Load Capacitance Output Current
- -
- -
10 0.1
pF mA
6.7.3.7. A/D Converter Reference
Symbol VVRT VVRTN
Parameter Reference Voltage Top Reference Voltage Top Noise
Pin Name VRT
Min. 2.5
Typ. 2.6
Max. 2.8 100
Unit V mVPP
Test Conditions 10 F/10 nF, 1 G Probe
-
-
Micronas
155
VCT 38xxA
6.7.3.8. Analog Video Front-End and A/D Converters
ADVANCE INFORMATION
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
Luma - Path (Composite) RVIN CVIN VVIN VVIN AGC DNLAGC VVINCL QCL ICL-LSB DNLICL Input Resistance Input Capacitance Full Scale Input Voltage Full Scale Input Voltage AGC step width AGC Differential Non-Linearity Input Clamping Level, CVBS VIN1-4 1 - 1.8 0.5 - - - - 5 2.0 0.6 0.166 - 1.0 - - 2.2 0.7 - M pF VPP VPP dB LSB V min. AGC Gain max. AGC Gain 6-Bit Resolution= 64 Steps fsig=1MHz, - 2 dBr of max. AGC-Gain Binary Level = 64 LSB min. AGC Gain 5 Bit - I-DAC, bipolar VVIN=1.5 V Code Clamp-DAC=0
0.5
-
Clamping DAC Resolution Input Clamping Current per step Clamping DAC Differential NonLinearity
-16 0.7 -
-
1.0 -
15 1.3
steps
A
LSB
0.5
Chroma - Path (Composite) RCIN VCIN VCINDC Input Resistance SVHS Chroma Full Scale Input Voltage, Chroma Input Bias Level, SVHS Chroma Binary Code for Open Chroma Input Chroma - Path (Component) RCIN CCIN VCIN VCIN VCINCL QCL ICL-LSB DNLICL Input Resistance Input Capacitance Full Scale Input Voltage Full Scale Input Voltage Input Clamping Level Cr, Cb Clamping DAC Resolution Input Clamping Current per step Clamping DAC Differential NonLinearity CRIN CBIN 1 CIN1 CIN2 1.4 1.08 2.0 1.2 1.5 128 2.6 1.32 k VPP V
- -
- -
-
- -
0,84 1.2 1.5
-
4.5 0.92 1.32
M pF VPP VPP V steps
Code Clamp-DAC=0
-
0.76 1.08
minimal Range extended Range Binary Level = 128 LSB 6 Bit - I-DAC, bipolar VVIN=1.5 V
-
-32 0.59
-
31 1.11
-
0.85
A
LSB
-
-
0.5
156
Micronas
ADVANCE INFORMATION
VCT 38xxA
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
Dynamic Characteristics for all Video-Paths (Luma + Chroma) BW XTALK THD Bandwidth Crosstalk, any Two Video Inputs Total Harmonic Distortion VIN1-4 CIN1-2 CBIN 8 - - 10 -56 50 - - - MHz dB dB -2 dBr input signal level 1 MHz, -2 dBr signal level 1 MHz, 5 harmonics, -2 dBr signal level 1 MHz, all outputs, -2 dBr signal level Code Density, DC-ramp
SINAD
Signal-to-Noise and Distortion Ratio Integral Non-Linearity Differential Non-Linearity Differential Gain Differential Phase
-
45
-
dB
INL DNL DG DP
- - - -
- - - -
1 0.8 3
1.5
LSB LSB % deg
-12 dBr, 4.4 MHz signal on DC-ramp
Micronas
157
VCT 38xxA
6.7.3.9. Analog RGB and FB Inputs
ADVANCE INFORMATION
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
RGB Input Characteristics VRGBIN VRGBIN VRGBIN External RGB Inputs Voltage Range nominal RGB Input Voltage peak-to-peak RGB Inputs Voltage for Maximum Output Current RIN GIN BIN
-0.3
-
1.1
V SCART Spec: 0.7V 3dB
0.5
0.7
1.0
VPP V V V
- - -
0.44 0.7 1.1
- - - -
13 0.5
Contrast setting: 511 Contrast setting: 323 Contrast setting: 204
tCLP CIN IIL VCLIP VCLAMP VINOFF VINOFF RCLAMP
Clamp Pulse Width Input Capacitance Input Leakage Current
1.6
- - -
s
pF
- -0.5 -
A
Clamping OFF, VIN = -0.3...3 V
RGB Input Voltage for Clipping Current Clamp Level at Input Offset Level at Input
2
-
V
40
60
80 10
mV mV
Clamping ON Extrapolated from VIN = 100 and 200 mV Extrapolated from VIN = 100 and 200 mV
-10 -10 -
- -
Offset Level Match at Input
10
mV
Clamping-ON-Resistance
140
-
Fast Blank Input Characteristics VFBLOFF VFBLON VFBLTRIG tPID FBLIN Low Level FBLIN High Level Fast Blanking Trigger Level typical Delay Fast Blanking to RGB OUT from midst of FBLIN-transition to 90% of RGBOUT- transition FBLIN
-
0.9
- -
0.7
0.5
V V V
- -
- -
8
15
ns
Internal RGB = 3.75 mA Full Scale Int. Brightness = 0 External Brightness = 1.5 mA (Full Scale) RGBin = 0 VFBLOFF = 0.4 V VFBLON = 1.0 V Rise and fall time = 2 ns
Difference of Internal Delay to External RGBin Delay Switch-Over-Glitch
-5 -
-
+5
ns
0.5
-
pAs
Switch from 3.75 mA (int) to 1.5 mA (ext)
158
Micronas
ADVANCE INFORMATION
VCT 38xxA
6.7.3.10. Horizontal Flyback Input
Symbol VIL VIH VIHST PSRRHF PSRRMF PSRRLF
Parameter Input Low Voltage Input High Voltage Input Hysteresis Power Supply Rejection Ratio of Trigger Level Power Supply Rejection Ratio of Trigger Level Power Supply Rejection Ratio of Trigger Level
Pin Name HFLB
Min. - 2.6 0.1 0
Typ. - - -
Max. 1.8 - -
Unit V V V dB
Test Conditions
- - -
- - -
f = 20 MHz
-20 -40
dB
f < 15 kHz
dB
f < 100 Hz
6.7.3.11. Horizontal Drive Output
Symbol VOL VOH tOF IOL
Parameter Output Low Voltage Output High Voltage (Open Drain Stage) Output Fall Time Output Low Current
Pin Name HOUT
Min.
Typ.
Max. 0.4 5
Unit V V
Test Conditions IOL = 10 mA external pull-up resistor
- - - -
- -
8
20 10
ns mA
CLOAD = 30pF
-
6.7.3.12. Vertical Safety Input
Symbol VILA VIHA VILB VIHB VIHST tPID
Parameter Input Low Voltage A Input High Voltage A Input Low Voltage B Input High Voltage B Input Hysteresis A and B Internal Delay
Pin Name SAFETY
Min.
Typ.
Max. 1.8
Unit V V V V V ns
Test Conditions
-
2.6
- - - - - -
-
3.0
-
3.8 0.1
- -
100
-
6.7.3.13. Vertical Protection Input
Symbol VIL VIH VIHST
Parameter Input Low Voltage Input High Voltage Input Hysteresis
Pin Name VPROT
Min.
Typ.
Max. 1.8
Unit V V V
Test Conditions
-
2.6 0.1
- - -
- -
Micronas
159
VCT 38xxA
6.7.3.14. Vertical and East/West D/A Converter Output
ADVANCE INFORMATION
Symbol VOMIN VOMAX IDACN PSRR
Parameter Minimum Output Voltage
Pin Name EW VERT VERTQ
Min.
Typ. 0
Max.
Unit V
Test Conditions Rload = 6.8 k Rxref = 10 k Rload = 6.8 k Rxref = 10 k Rxref = 10 k
-
-
Maximum Output Voltage
2.82
3
3.2
V
Full scale DAC Output Current Power Supply Rejection Ratio
415
440
465
A
-
20
-
dB
6.7.3.15. Interlace Output
Symbol VOL VOH
Parameter Output Low Voltage Output High Voltage
Pin Name INTLC
Min.
Typ. 0.2 VSUPAB - 0.2
Max. 0.4
Unit V V
Test Conditions IOL = 1.6 mA
-
VSUPAB - 0.4
-
-IOL = 1.6mA
6.7.3.16. Sense A/D Converter Input
Symbol VI VI255 C0
Parameter Input Voltage Range
Pin Name SENSE 0
Min.
Typ.
Max. VSUPA
B
Unit V
Test Conditions
-
Input Voltage for code 255
1.4
1.54
1.7
V
Read cutoff blue register Offset check, read cutoff blue register
Digital Output for zero Input
-
-
16
LSB
RI
Input Impedance
1
-
-
M
6.7.3.17. Range Switch Output
Symbol RON IMax ILEAK CIN
Parameter Output On Resistance Maximum Current Leakage Current Input Capacitance
Pin Name RSW1 RSW2
Min.
Typ.
Max. 50 15 600 5
Unit
Test Conditions IOL = 10 mA
- - - -
- - - -
mA nA pF
RSW High Impedance
160
Micronas
ADVANCE INFORMATION
VCT 38xxA
6.7.3.18. D/A Converter Reference
Symbol VDACREF VDACR VXREF
Parameter DAC-Ref. Voltage DAC-Ref. Output resistance DAC-Ref. Voltage Bias Current Generation
Pin Name VRD
Min. 2.38 18
Typ. 2.50 25
Max. 2.67 32
Unit V k
Test Conditions
XREF
2.38
2.5
2.67
V
Rxref = 10 k
6.7.3.19. Analog RGB Outputs, D/A Converters
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
Internal RGB Signal D/A Converter Characteristics Resolution IOUT IOUT IOUT IOUT IOUT IOUT IOUT IOUT Full Scale Output Current Differential Nonlinearity Integral Nonlinearity Glitch Pulse Charge ROUT GOUT BOUT
-
3.6
10 3.75
-
3.9 0.5 1
bit mA LSB LSB pAs Ramp signal, 25 output termination 10% to 90%, 90% to 10% 2/2.5MHz full scale Signal: 1MHz full scale Bandwidth: 10MHz Rref = 10 k
- - - - -
+50
- -
0.5
- - -50 -
Rise and Fall Time Intermodulation Signal to Noise
3
ns dB dB
- - - -
Matching R-G, R-B, G-B R/B/G Crosstalk one channel talks two channels talk RGB Input Crosstalk from external RGB one channel talks two channels talk three channels talk
-2 -
2
% dB Passive channel: IOUT =1.88 mA Crosstalk-Signal: 1.25 MHz, 3.75 mA PP
-46
- - -
- - -
-50 -50 -50
dB dB dB
Internal RGB Brightness D/A Converter Characteristics Resolution IBR IBR IBR IBR IBR IBR Full Scale Output Current relative Full Scale Output Current absolute Differential Nonlinearity Integral Nonlinearity Match R-G, R-B, G-B Match to digital RGB R-R, G-G, B-B ROUT GOUT BOUT
-
39.2
9 40
-
40.8
bit % Ref to max. digital RGB
- - - -2 -2
1.5
-
mA
- - - -
1 2 2 2
LSB LSB % %
Micronas
161
VCT 38xxA
ADVANCE INFORMATION
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
External RGB Voltage/Current Converter Characteristics Resolution IEXOUT Full Scale Output Current relative Full Scale Output Current absolute CR Contrast Adjust Range Gain Match R-G, R-B, G-B ROUT GOUT BOUT
-
96
9 100
-
104
bit % Ref. to max. Digital RGB VIN = 0.7 VPP, contrast = 323 Same as Digital RGB
- - -3 -3 -
3.75
- -
3
mA
16:511
- - -
%
Measured at RGB Outputs VIN = 0.7 V, contrast = 323 Measured at RGB Outputs VIN = 0.7 V, contrast = 323 Passive channel: VIN = 0.7V, contrast = 323 Crosstalk signal: 1.25 MHz, 3.75 mAPP
Gain Match to RGB-DACs R-R, G-G, B-B R/B/G Input Crosstalk one channel talks two channels talk
3
%
-46
dB
RGB Input Crosstalk from Internal RGB one channel talks two channels talk tree channels talk RGB Input Noise and Distortion
-
-
-50
dB
-
-
-50
dB
VIN=0.7 VPP at 1 MHz contrast = 323 Bandwidth: 10 MHz VIN = 0.7 VPP, contrast =323 Input signal 1 MHz Input signal 6 MHz VIN = 0.7 VPP contrast =323 VIN = 0.44V
RGB Input Bandwidth -3dB
15
- - -
MHz
RGB Input THD
- -
-50 -40
dB dB
Differential Nonlinearity of Contrast Adjust Integral Nonlinearity of Contrast Adjust VRGBO R,G,B Output Voltage R,G,B Output Load Resistance VOUTC RGB Output Compliance
- - -1.0 - -1.5
- - - - -1.3
1
LSB
2
LSB
0.3 100
V
Referred to VSUPO Ref. to VSUPO Ref. to VSUPO Sum of max. Current of RGB-DACs and max. Current of Int. Brightness DACs is 2% degraded
V
-1.2
162
Micronas
ADVANCE INFORMATION
VCT 38xxA
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
External RGB Brightness D/A Converter Characteristics Resolution IEXBR Full Scale Output Current relative Full Scale Output Current absolute Differential Nonlinearity Integral Nonlinearity Matching R-G, R-B, G-B Matching to digital RGB R-R, GG, B-B RGB Output Cutoff D/A Converter Characteristics Resolution ICUT Full Scale Output Current relative Full Scale Output Current absolute Differential nonlinearity Integral nonlinearity Matching to digital RGB R-R, GG, B-B RGB Output Ultrablack D/A Converter Characteristics Resolution IUB Full Scale Output Current relative ROUT GOUT BOUT ROUT GOUT BOUT ROUT GOUT BOUT
-
39.2
9 40
-
40.8
bit % Ref to max. digital RGB
- - - -2 -2
1.5
-
mA
- - - -
1 2 2 2
LSB LSB % %
-
58.8
9 60
-
61.2
bit % Ref to max. digital RGB
- - - -2
2.25
-
mA
- - -
1 2 2
LSB LSB %
-
19.6
1 20
-
20.4
bit % Ref to max. digital RGB
Full Scale Output Current absolute Match to digital RGB R-R, G-G, B-B
- -2
0.75
-
mA
-
2
%
Micronas
163
VCT 38xxA
6.7.3.20. Scan Velocity Modulation Output
ADVANCE INFORMATION
Symbol
Parameter Resolution
Pin Name SVMOUT
Min.
Typ. 8 1.875
Max.
Unit bit mA LSB LSB pAs
Test Conditions
-
1.55
-
2.25 0.5 1
IOUT IOUT IOUT IOUT IOUT
Full Scale Output Current Differential Nonlinearity Integral Nonlinearity Glitch Pulse Charge
- - - -
- -
0.5
- -
Ramp, output line is terminated on both ends with 50 10% to 90%, 90% to 10%
Rise and Fall Time
3
ns
6.7.3.21. Analog Audio Inputs and Outputs
Symbol RAIN dVAOUT AAudio frAudio
Parameter Audio Input Resistance Deviation of DC-Level at Audio Output from GNDAB Voltage Gain from Audio Input to Audio Output Frequency Response from Audio Input to Audio Output bandwidth: 50 Hz to 15000 Hz Power Supply Rejection Ratio for Audio Output
Pin Name AIN1-3 AOUT1-2
Min. 25
Typ. 40
Max. 58 +20
Unit k mV
Test Conditions fsignal = 1 kHz, I = 0.05 mA
-20 -1.0 -0.5
-
0.0
+0.5
dB
fsignal = 1 kHz AVOL = 0dB with resp. to 1 kHz
0.0
+0.5
dB
PSRR
tbd tbd
50 20
tbd
- -
20
dB dB
V
1 kHz sine at 100 mVRMS
100 kHz sine at 100 mVRMS
RGEN = 1k, equally weighted 50 Hz...15 kHz AVOL = mute, equally weighted 50 Hz...15 kHz Input Level = 0.7VRMS, fsig = 1 kHz, equally weighted 50 Hz...15 kHz Input Level = 0.7VRMS, fsig = 1 kHz, equally weighted 50 Hz...15 kHz, unused analog inputs connected to ground by Z < 1 k
VNOISE
Noise Output Voltage
-
VMute
Mute Output Voltage
-
tbd
2
V
THD
Total Harmonic Distortion from Audio Input to Audio Output
-
-
0.1
%
XTALK
Crosstalk attenuation between Audio Input and Audio Output
70
-
-
dB
164
Micronas
ADVANCE INFORMATION
VCT 38xxA
6.7.3.22. ADC Input Port
Symbol VREF
Parameter ADC Comparator Reference Voltage ADC Comparator Hysteresis, symmetrical to VREF ADC Comparator Delay Time LSB Value
Pin Name Px.y
Min.
Typ. 0.5* VSUPS 0.17
Max.
Unit V
Test Conditions
-
-
Vlh- Vhl tCDEL LSB
0.1
0.24
V
- -
-
VSUPS /1024
100
ns V
Overdrive=50mV
-
R A
Conversion Range Conversion Result
GNDS
-
INT (Vin/ LSB)
VSUPS
V hex GNDS-
-
000
- -
-
3FF
hex hex
Vin<=GNDS Vin>=VSUPS
-
tc ts TUE DNL Ci Conversion Time Sample Time Total Unadjusted Error Differential Non-Linearity Input Capacitance during Sampling Period Serial Input Resistance during Sampling Period
- - -6 -3 - -
4 2
- -
15
-
s s
LSB LSB pF
-
6 3
- -
Ri
5
k
6.7.3.23. Universal Port
Symbol Vol
Parameter Output Low Voltage
Pin Name P1x P2x P3x
Min.
Typ.
Max. 0.4 1.0
Unit V
Test Conditions Io=3mA Io=10mA Io=-3mA Io=-10mA
-
VSUPP-0.4 VSUPP-1.0
- - - - -
Voh
Output High Voltage
-
V
VIL VIH Ii
Input Low Voltage Input High Voltage Input Leakage Current
P1x P2x P3x P42-P46
-
2.0
0.8
V V
-
0.1
-0.1
A
0Micronas
165
VCT 38xxA
6.7.3.24. Memory Port
ADVANCE INFORMATION
Symbol tCYC tADS
Parameter PH2 Cycle Time Address Setup Time
Pin Name
Min. -
Typ. 98.77 15 + 0.5 20 30 8 9 + 0.5 14 24 6 6 6
Max. 19 + 0.7 26 40 10 14 + 0.7 21 35 8 10 9
Unit ns ns ns/pf ns ns ns ns ns/ pF ns ns ns ns ns ns ns
Test Conditions
ADB[18-0]
-
CADB = 0 pF CADB = 10 pF CADB = 30 pF CADB = 10 pF CDB = 0 pF CDB = 10 pF CDB = 30 pF CDB = 0 pF
tADH tDWS
Address Hold Time Data Write Setup Time DB[7:0]
-
tDWH tDRS tDRH tENS tENH
Data Write Hold Time Data Read Setup Time Data Read Hold Time Enable Setup Time Enable Hold Time OE1Q OE2Q WE1Q WE2Q
12 6 -
COEQ,WEQ = 0 pF COEQ,WEQ = 0 pF
tcyc PH2 tADS tADH ADB[18:0] tACC tDRH DB[7:0] tDWH DB[7:0] tENS tDWS WRITE DATA tENH tDRS READ DATA
WEQ, OEQ
Fig. 6-33: Memory port timing
166
Micronas
ADVANCE INFORMATION
VCT 38xxA
7. Application
Fig. 7-1: VCT 38xxA application circuit, part 1/3
Micronas
167
VCT 38xxA
ADVANCE INFORMATION
Fig. 7-2: VCT 38xxA application circuit, part 2/3
168
Micronas
ADVANCE INFORMATION
VCT 38xxA
Fig. 7-3: VCT 38xxA application circuit, part 3/3
Micronas
169
VCT 38xxA
ADVANCE INFORMATION
170
Micronas
ADVANCE INFORMATION
VCT 38xxA
9. References 1. Preliminary Data Sheet: "VDP 31xxB", Sept. 25, 1998 6251-437-2PD 2. Preliminary Data Sheet: "TPU 3035, TPU 3040, TPU 3050", Feb. 23, 1999 6251-349-6PD 3. Preliminary Data Sheet: "W65C02", Oct. 2, 1991 6251-364-1PD 4."Enhanced Teletext Specification". European Telecommunication Standard ETS 300 706. ETSI, May1997. 5. "Television systems; 625-line television Wide Screen Signalling (WSS)". European Telecommunication Standard ETS 300 294. ETSI, May1996. 6. "Television systems; Specification of the domestic video Programme Delivery Control system (PDC)". European Telecommunication Standard ETS 300 231. ETSI, August1996. 7. "Electronic Programme Guide (EPG)". European Telecommunication Standard ETS 300 707. ETSI, May1997.
8. Glossary of Abbreviations AIT BTT BTTL CCU CLUT CPU CRI DMA DRAM FLOF FRC MPT MPET NMI OSD PDC PLT RAM ROM SRAM TOP TPU TTX VBI VPS WSS WST Additional Information Table Basic TOP Table Basic TOP Table List Central Control Unit Color Look Up Table Central Processing Unit Clock Running-in Direct Memory Access Dynamic Random Access Memory Full Level One Features Framing Code Multipage Table Multipage Extension Table Non Maskable Interrupt On Screen Display Programme Delivery Control Page Linking Table Random Access Memory Read Only Memory Static Random Access Memory Table Of Pages Teletext Processing Unit Teletext Vertical Blanking Interval Video-Programm-System Wide Screen Signalling World System Teletext
Micronas
171
VCT 38xxA
10. Data Sheet History 1. Advance Information: "VCT 38xxA Video/Controller/ Teletext IC Family", Edition Oct. 17, 2000, 6251-518-1AI. First release of the advance information.
ADVANCE INFORMATION
Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-518-1AI
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
172
Micronas

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